Comparison of CPU architectures - AbsoluteAstronomy.com

Bits

In computer science and engineering, computer architecture is the practical art of selecting and interconnecting hardware components to create computers that meet functional, performance and cost goals and the formal modelling of those systems....

s are often described as n-bit architectures. Today n is often 8, 16, 32, or 64, but other sizes have been used. This is actually a strong simplification. A computer architecture often has a few more or less "natural" datasizes in the instruction set

Instruction set

An instruction set, or instruction set architecture , is the part of the computer architecture related to programming, including the native data types, instructions, registers, addressing modes, memory architecture, interrupt and exception handling, and external I/O...

, but the hardware implementation of these may be very different. Many architectures have instructions operating on half and/or twice the size of respective processors major internal datapaths. Examples of this are the 8080, Z80, MC68000 as well as many others. On this type of implementations, a twice as wide operation typically also takes around twice as many clock cycles (which is not the case on high performance implementations). On the 68000, for instance, this means 8 instead of 4 clock ticks, and this particular chip may be described as a 32-bit architecture with a 16-bit implementation. The external databus width is often not useful to determine the width of the architecture; the NS32008, NS32016 and NS32032 were basically the same 32-bit chip with different external data buses. The NS32764 had a 64-bit bus, but used 32-bit registers.

The width of addresses may or may not be different than the width of data.
Early 32-bit microprocessors often had a 24-bit address, as did the System/360

System/360

The IBM System/360 was a mainframe computer system family first announced by IBM on April 7, 1964, and sold between 1964 and 1978. It was the first family of computers designed to cover the complete range of applications, from small to large, both commercial and scientific...

processors.

Operands

The number of operands is one of the factors that may give an indication about the performance of the instruction set.
A three-operand architecture will allow
A := B + C
to be computed in one instruction.

A two-operand architecture will allow
A := A + B
to be computed in one instruction, so two instructions will need to be executed to simulate a single three-operand instruction
A := B
A := A + C

Endianess

An architecture may use "big" or "little" endianness, or both, or be configurable to use either. Little endian processors order bytes in memory with the least significant byte of a multi-byte value in the lowest-numbered memory location. Big endian architectures instead order them with the most significant byte at the lowest-numbered address. The x86 and the ARM architectures as well as several 8-bit architectures are little endian. Most RISC architectures (SPARC, Power, PowerPC, MIPS) were originally big endian, but many (including ARM) are now configurable.

Architectures

The table below compares basic information about CPU architectures.

Architecture	Bits	Version	Introduced	Max # Operand Operand In mathematics, an operand is the object of a mathematical operation, a quantity on which an operation is performed.-Example :The following arithmetic expression shows an example of operators and operands:3 + 6 = 9\;... s	Type	Design	Registers Processor register In computer architecture, a processor register is a small amount of storage available as part of a CPU or other digital processor. Such registers are addressed by mechanisms other than main memory and can be accessed more quickly...	Instruction encoding	Branch Branch (computer science) A branch is sequence of code in a computer program which is conditionally executed depending on whether the flow of control is altered or not . The term can be used when referring to programs in high level languages as well as program written in machine code or assembly language... Evaluation	Endianness Endianness In computing, the term endian or endianness refers to the ordering of individually addressable sub-components within the representation of a larger data item as stored in external memory . Each sub-component in the representation has a unique degree of significance, like the place value of digits...	Extensions
Alpha DEC Alpha Alpha, originally known as Alpha AXP, is a 64-bit reduced instruction set computer instruction set architecture developed by Digital Equipment Corporation , designed to replace the 32-bit VAX complex instruction set computer ISA and its implementations. Alpha was implemented in microprocessors...	64		1992	3	Register-Register	RISC Reduced instruction set computer Reduced instruction set computing, or RISC , is a CPU design strategy based on the insight that simplified instructions can provide higher performance if this simplicity enables much faster execution of each instruction. A computer based on this strategy is a reduced instruction set computer...	32	Fixed	Condition register	Bi	, , ,
ARM ARM architecture ARM is a 32-bit reduced instruction set computer instruction set architecture developed by ARM Holdings. It was named the Advanced RISC Machine, and before that, the Acorn RISC Machine. The ARM architecture is the most widely used 32-bit ISA in numbers produced...	32	ARMv7 and earlier	1983	3	Register-Register	RISC	16	Fixed (32-bit), Thumb: Fixed (16-bit), Thumb-2: Variable (16 and 32-bit)	Condition code	Bi	NEON, Jazelle Jazelle Jazelle DBX allows some ARM processors to execute Java bytecode in hardware as a third execution state alongside the existing ARM and Thumb modes. Jazelle functionality was specified in the ARMv5TEJ architecture and the first processor with Jazelle technology was the ARM926EJ-S... , , TrustZone,
ARM ARM architecture ARM is a 32-bit reduced instruction set computer instruction set architecture developed by ARM Holdings. It was named the Advanced RISC Machine, and before that, the Acorn RISC Machine. The ARM architecture is the most widely used 32-bit ISA in numbers produced...	64	ARMv8	TBA	3	Register-Register	RISC	30	Fixed (32-bit), Thumb: Fixed (16-bit), Thumb-2: Variable (16 and 32-bit), A64	Condition code	Bi	NEON, Jazelle Jazelle Jazelle DBX allows some ARM processors to execute Java bytecode in hardware as a third execution state alongside the existing ARM and Thumb modes. Jazelle functionality was specified in the ARMv5TEJ architecture and the first processor with Jazelle technology was the ARM926EJ-S... , , TrustZone
AVR32 AVR32 The AVR32 is a 32-bit RISC microprocessor architecture designed by Atmel. The microprocessor architecture was designed by a handful of people educated at the Norwegian University of Science and Technology, including lead designer Øyvind Strøm, PhD and CPU architect Erik Renno, M.Sc in Atmel's...	32	Rev 2	2006	2-3		RISC	15	Variable		Big	Java Virtual Machine Java Virtual Machine A Java virtual machine is a virtual machine capable of executing Java bytecode. It is the code execution component of the Java software platform. Sun Microsystems stated that there are over 4.5 billion JVM-enabled devices.-Overview:...
Blackfin Blackfin The Blackfin is a family of 16- or 32-bit microprocessors developed, manufactured and marketed by Analog Devices. The family is characterized by their built-in, fixed-point digital signal processor functionality supplied by 16-bit Multiply–accumulates , accompanied on-chip by a small and...	32		2000			RISC	8			Little
DLX DLX The DLX is a RISC processor architecture designed by John L. Hennessy and David A. Patterson, the principal designers of the MIPS and the Berkeley RISC designs , the two benchmark examples of RISC design. The DLX is essentially a cleaned up and simplified MIPS, with a simple 32-bit load/store...	32		1990	3		RISC	32	Fixed (32-bit)		Big
eSi-RISC ESi-RISC eSi-RISC is a configurable CPU architecture from EnSilica. It is currently available in three different implementations: the eSi-1600, eSi-3200 and eSi-3250. The eSi-1600 features a 16-bit data-path, while the eSi-3200 and eSi-3250 feature 32-bit data-paths...	16/32		2009	3	Register-Register	RISC	8-72	Variable(16 or 32-bit)	Compare and branch and condition register	Bi	User-defined instructions
Itanium Itanium Itanium is a family of 64-bit Intel microprocessors that implement the Intel Itanium architecture . Intel markets the processors for enterprise servers and high-performance computing systems... (IA-64)	64		2001		Register-Register	EPIC Explicitly Parallel Instruction Computing Explicitly parallel instruction computing is a term coined in 1997 by the HP–Intel alliance to describe a computing paradigm that researchers had been investigating since the early 1980s. This paradigm is also called Independence architectures...	128		Condition register	Bi (selectable)	Intel Virtualization Technology
M32R M32R The M32R is a 32-bit RISC instruction set architecture developed by Mitsubishi for embedded microprocessors and microcontrollers. The ISA is now owned by Renesas Electronics Corporation, and the company designs and fabricates M32R implementations. M32R processors are used in embedded systems such...	32		1997			RISC	16	Fixed (16- or 32-bit)		Bi
m68k Motorola 68000 The Motorola 68000 is a 16/32-bit CISC microprocessor core designed and marketed by Freescale Semiconductor...	16/32		1979			CISC Complex instruction set computer A complex instruction set computer , is a computer where single instructions can execute several low-level operations and/or are capable of multi-step operations or addressing modes within single instructions...	16			Big
Mico32 LatticeMico32 LatticeMico32 is a 32-bit microprocessor soft core from Lattice Semiconductor optimized for field-programmable gate arrays . It uses a Harvard architecture, which means the instruction and data buses are separate. Bus arbitration logic can be used to combine the two buses, if desired.LatticeMico32...	32		2006	3	Register-Register	RISC	32	Fixed (32-bit)	Compare and branch	Big	User-defined instructions
MIPS MIPS architecture MIPS is a reduced instruction set computer instruction set architecture developed by MIPS Technologies . The early MIPS architectures were 32-bit, and later versions were 64-bit...	64 (32→64)	5	1981	3	Register-Register	RISC	32	Fixed (32-bit)	Condition register	Bi	MDMX MDMX The MDMX , also known as MaDMaX, is an extension to the MIPS instruction set architecture released in October 1996 at the Microprocessor Forum.- History :... , MIPS-3D MIPS-3D MIPS-3D is an extension to the MIPS V instruction set architecture that added 13 new instructions for improving the performance of 3D graphics applications...
MMIX MMIX MMIX is a 64-bit RISC instruction set architecture designed by Donald Knuth, with significant contributions by John L. Hennessy and Richard L. Sites...	64		1999	3	Register-Register	RISC	256	Fixed (32-bit)		Big
PA-RISC PA-RISC PA-RISC is an instruction set architecture developed by Hewlett-Packard. As the name implies, it is a reduced instruction set computer architecture, where the PA stands for Precision Architecture... (HP/PA)	64 (32→64)	2.0	1986	3		RISC	32	Fixed	Compare and branch	Big	Multimedia Acceleration eXtensions Multimedia Acceleration eXtensions The Multimedia Acceleration eXtensions or MAX are instruction set extensions to the Hewlett-Packard PA-RISC instruction set architecture .... (MAX), MAX-2
PowerPC PowerPC PowerPC is a RISC architecture created by the 1991 Apple–IBM–Motorola alliance, known as AIM...	32/64 (32→64)	2.06	1991	3	Register-Register	RISC	32	Fixed, Variable	Condition code	Big/Bi	AltiVec AltiVec AltiVec is a floating point and integer SIMD instruction set designed and owned by Apple, IBM and Freescale Semiconductor, formerly the Semiconductor Products Sector of Motorola, , and implemented on versions of the PowerPC including Motorola's G4, IBM's G5 and POWER6 processors, and P.A. Semi's... , APU, VSX, Cell Cell (microprocessor) Cell is a microprocessor architecture jointly developed by Sony, Sony Computer Entertainment, Toshiba, and IBM, an alliance known as "STI". The architectural design and first implementation were carried out at the STI Design Center in Austin, Texas over a four-year period beginning March 2001 on a...
S+core S+core S+core is a hybrid 32/16-bit instruction set architecture by Sunplus Technology.It is supported by the Linux kernel since version 2.6.32.The microarchitecture features Advanced Microcontroller Bus Architecture support and includes SJTAG for In-circuit emulation.It is implemented on the Sunplus...	32/16-bit		2005			RISC				Little
Series 32000	32		1982	5	Memory-Memory	CISC	8	Variable Huffman coded, up to 23 bytes long	Condition Code	Little	BitBlt instructions
SPARC SPARC SPARC is a RISC instruction set architecture developed by Sun Microsystems and introduced in mid-1987....	64 (32→64)	V9	1985	3	Register-Register	RISC	32	Fixed	Condition code	Big → Bi	VIS Visual Instruction Set Visual Instruction Set, or VIS, is a SIMD instruction set for SPARC V9 microprocessors developed by Sun Microsystems. There are three versions of VIS: VIS 1, VIS 2 and VIS 2+... 1.0, 2.0, 3.0
SuperH SuperH SuperH is a 32-bit reduced instruction set computer instruction set architecture developed by Hitachi. It is implemented by microcontrollers and microprocessors for embedded systems.... (SH)	32		1990s	2	Register-Register/ Register-Memory	RISC	16	Fixed	Condition Code (Single Bit)	Bi
System/360 System/360 The IBM System/360 was a mainframe computer system family first announced by IBM on April 7, 1964, and sold between 1964 and 1978. It was the first family of computers designed to cover the complete range of applications, from small to large, both commercial and scientific... / System/370 System/370 The IBM System/370 was a model range of IBM mainframes announced on June 30, 1970 as the successors to the System/360 family. The series maintained backward compatibility with the S/360, allowing an easy migration path for customers; this, plus improved performance, were the dominant themes of the... / z/Architecture Z/Architecture z/Architecture, initially and briefly called ESA Modal Extensions , refers to IBM's 64-bit computing architecture for IBM mainframe computers. IBM introduced its first z/Architecture-based system, the zSeries Model 900, in late 2000. Later z/Architecture systems include the IBM z800, z990, z890,...	64 (32→64)	3	1964		Register-Memory/Memory-Memory	CISC	16	Fixed	Condition code	Big
VAX VAX VAX was an instruction set architecture developed by Digital Equipment Corporation in the mid-1970s. A 32-bit complex instruction set computer ISA, it was designed to extend or replace DEC's various Programmed Data Processor ISAs...	32		1977	6	Memory-Memory	CISC	16	Variable	Compare and branch	Little	VAX Vector Architecture
x86	32 (16→32)		1978	2	Register-Memory	CISC	16	Variable	Condition code	Little	MMX, 3DNow! 3DNow! 3DNow! is an extension to the x86 instruction set developed by Advanced Micro Devices . It adds single instruction multiple data instructions to the base x86 instruction set, enabling it to perform simple vector processing, which improves the performance of many graphic-intensive applications... , SSE Streaming SIMD Extensions In computing, Streaming SIMD Extensions is a SIMD instruction set extension to the x86 architecture, designed by Intel and introduced in 1999 in their Pentium III series processors as a reply to AMD's 3DNow! . SSE contains 70 new instructions, most of which work on single precision floating point... , PAE Physical Address Extension In computing, Physical Address Extension is a feature to allow x86 processors to access a physical address space larger than 4 gigabytes.... ,
x86-64 X86-64 x86-64 is an extension of the x86 instruction set. It supports vastly larger virtual and physical address spaces than are possible on x86, thereby allowing programmers to conveniently work with much larger data sets. x86-64 also provides 64-bit general purpose registers and numerous other...	64		2003	2	Register-Memory	CISC	32	Variable	Condition code	Little	MMX, 3DNow! 3DNow! 3DNow! is an extension to the x86 instruction set developed by Advanced Micro Devices . It adds single instruction multiple data instructions to the base x86 instruction set, enabling it to perform simple vector processing, which improves the performance of many graphic-intensive applications... , PAE Physical Address Extension In computing, Physical Address Extension is a feature to allow x86 processors to access a physical address space larger than 4 gigabytes.... , AVX Advanced Vector Extensions Advanced Vector Extensions is an extension to the x86 instruction set architecture for microprocessors from Intel and AMD proposed by Intel in March 2008 and first supported by Intel with the Westmere processor shipping in Q1 2011 and now by AMD with the Bulldozer processor shipping in Q3 2011.AVX...

Microarchitectures

The following table compares specific microarchitecture

Microarchitecture

In computer engineering, microarchitecture , also called computer organization, is the way a given instruction set architecture is implemented on a processor. A given ISA may be implemented with different microarchitectures. Implementations might vary due to different goals of a given design or...

Microarchitecture	Pipeline stages	Misc
AMD K5 AMD K5 The K5 was AMD's first x86 processor to be developed entirely in-house. Introduced in March 1996, its primary competition was Intel's Pentium microprocessor. The K5 was an ambitious design, closer to a Pentium Pro than a Pentium regarding technical solutions and internal architecture...		Out-of-order execution, register renaming, speculative execution
AMD K6 AMD K6 The K6 microprocessor was launched by AMD in 1997. The main advantage of this particular microprocessor is that it was designed to fit into existing desktop designs for Pentium branded CPUs. It was marketed as a product which could perform as well as its Intel Pentium II equivalent but at a...		Superscalar, branch prediction
AMD K6-III AMD K6-III The K6-III, code-named "Sharptooth", was an x86 microprocessor manufactured by AMD, released on 22 February 1999, with 400 and 450 MHz models. It was the last Socket 7 desktop processor. For an extremely short time after its release, the fastest available desktop processor from Intel was the...		Branch prediction, speculative execution, out-of-order execution
AMD K7 Athlon Athlon is the brand name applied to a series of x86-compatible microprocessors designed and manufactured by Advanced Micro Devices . The original Athlon was the first seventh-generation x86 processor and, in a first, retained the initial performance lead it had over Intel's competing processors...		Out-of-order execution, branch prediction, Harvard architecture
AMD K8 AMD K8 The AMD K8 is a computer processor microarchitecture designed by AMD as the successor to the AMD K7 microarchitecture. The K8 was the first implementation of the AMD64 64-bit extension to the x86 processor architecture.Processors based on the K8 core include:...		64-bit, integrated memory controller, 16 byte instruction prefetching
AMD K10 AMD K10 The AMD Family 10h is a microprocessor microarchitecture by AMD. Though there were once reports that the K10 had been canceled, the first third-generation Opteron products for servers were launched on September 10, 2007, with the Phenom processors for desktops following and launching on November...		Superscalar, out-of-order execution, 32-way set associative L3 victim cache, 32-byte instruction prefetching
ARM7TDMI(-S)	3
ARM7EJ-S	5
ARM810	5
ARM9TDMI	5
ARM1020E	6
XScale PXA210/PXA250 XScale The XScale, a microprocessor core, is Intel's and Marvell's implementation of the ARMv5 architecture, and consists of several distinct families: IXP, IXC, IOP, PXA and CE . Intel sold the PXA family to Marvell Technology Group in June 2006....	7
ARM1136J(F)-S ARM11 ARM11 is an ARM architecture 32-bit RISC microprocessor family which introduced the ARMv6 architectural additions. These include SIMD media instructions, multiprocessor support and a new cache architecture...	8
ARM1156T2(F)-S ARM11 ARM11 is an ARM architecture 32-bit RISC microprocessor family which introduced the ARMv6 architectural additions. These include SIMD media instructions, multiprocessor support and a new cache architecture...	9
ARM Cortex-A5	8
ARM Cortex-A8 ARM Cortex-A8 The ARM Cortex-A8 is a processor core designed by ARM Holdings implementing the ARM v7 instruction set architecture. Compared to the ARM11 core, the Cortex-A8 is dual-issue superscalar, achieving roughly twice the instructions executed per clock cycle....	13
ARM Cortex-A9		Out-of-order, speculative issue, superscalar
ARM Cortex-A15		Multicore (up to 16)
AVR32 AP7	7
AVR32 UC3	3	Harvard architecture
Bobcat Bobcat (processor) Bobcat is the latest x86 processor core from AMD aimed at low-power / low-cost market.It was revealed during a speech from AMD executive vice-president Henri Richard in Computex 2007 and was put into production Q1 2011. One of the major supporters was executive vice-president Mario A...		Out-of-order execution
Bulldozer Bulldozer (processor) Bulldozer is the codename Advanced Micro Devices has given to one of the next-generation CPU cores after the K10 microarchitecture for the company's M-SPACE design methodology, with the core specifically aimed at 10-watt to 125-watt TDP computing products. Bulldozer is a completely new design...		Shared L3 cache, multithreading, multicore, integrated memory controller
Crusoe Transmeta Crusoe The Crusoe is a family of x86-compatible microprocessors developed by Transmeta. Crusoe was notable for its method of achieving x86 compatibility. Instead of the instruction set architecture being implemented in hardware, or translated by specialized hardware, the Crusoe runs a software abstraction...		In-order execution, 128-bit VLIW, integrated memory controller
Efficeon Efficeon The Efficeon processor is Transmeta's second-generation 256-bit VLIW design which employs a software engine to convert code written for x86 processors to the native instruction set of the chip...		In-order execution, 256-bit VLIW, fully integrated memory controller
Cyrix Cx5x86 Cyrix Cx5x86 Released in August 1995, four months before the more famous Cyrix 6x86, the Cyrix 5x86 was one of the fastest CPUs ever produced for Socket 3 computer systems...	6	Branch prediction
Cyrix 6x86 Cyrix 6x86 The Cyrix 6x86 is a sixth-generation, 32-bit 80x86-compatible microprocessor designed by Cyrix and manufactured by IBM and SGS-Thomson. It was originally released in 1996.-Architecture:...		Superscalar, superpipelined, register renaming, speculative execution, out-of-order execution
DLX DLX The DLX is a RISC processor architecture designed by John L. Hennessy and David A. Patterson, the principal designers of the MIPS and the Berkeley RISC designs , the two benchmark examples of RISC design. The DLX is essentially a cleaned up and simplified MIPS, with a simple 32-bit load/store...	5
EV4 (Alpha 21064) Alpha 21064 The Alpha 21064 is a microprocessor developed and fabricated by Digital Equipment Corporation that implemented the Alpha instruction set architecture . It was introduced as the DECchip 21064 before it was renamed in 1994. The 21064 is also known by its code name, EV4...		Superscalar
EV7 (Alpha 21364) Alpha 21364 The Alpha 21364, code-named "Marvel", also known as EV7 is a microprocessor developed by Digital Equipment Corporation , later Compaq Computer Corporation, that implemented the Alpha instruction set architecture .- History :...		Superscalar design with out-of-order execution, branch prediction, 4-way SMT, integrated memory controller
EV8 (Alpha 21464) Alpha 21464 The Alpha 21464 is an unfinished microprocessor that implements the Alpha instruction set architecture developed by Digital Equipment Corporation and later by Compaq after it acquired Digital. The microprocessor was also known as EV8 or Araña, the latter being its code-name...		Superscalar design with out-of-order execution Out-of-order execution In computer engineering, out-of-order execution is a paradigm used in most high-performance microprocessors to make use of instruction cycles that would otherwise be wasted by a certain type of costly delay...
P5 P5 (microarchitecture) The original Pentium microprocessor was introduced on March 22, 1993. Its microarchitecture, deemed P5, was Intel's fifth-generation and first superscalar x86 microarchitecture. As a direct extension of the 80486 architecture, it included dual integer pipelines, a faster FPU, wider data bus,... (Pentium)	5	Superscalar
P6 P6 (microarchitecture) The P6 microarchitecture is the sixth generation Intel x86 microarchitecture, implemented by the Pentium Pro microprocessor that was introduced in November 1995. It is sometimes referred to as i686. It was succeeded by the NetBurst microarchitecture in 2000, but eventually revived in the Pentium M... (Pentium Pro Pentium Pro The Pentium Pro is a sixth-generation x86 microprocessor developed and manufactured by Intel introduced in November 1, 1995 . It introduced the P6 microarchitecture and was originally intended to replace the original Pentium in a full range of applications... )	14	Speculative execution, Register renaming, superscalar design with out-of-order execution Out-of-order execution In computer engineering, out-of-order execution is a paradigm used in most high-performance microprocessors to make use of instruction cycles that would otherwise be wasted by a certain type of costly delay...
P6 (Pentium II Pentium II The Pentium II brand refers to Intel's sixth-generation microarchitecture and x86-compatible microprocessors introduced on May 7, 1997. Containing 7.5 million transistors, the Pentium II featured an improved version of the first P6-generation core of the Pentium Pro, which contained 5.5 million... )		Branch prediction
P6 (Pentium III Pentium III The Pentium III brand refers to Intel's 32-bit x86 desktop and mobile microprocessors based on the sixth-generation P6 microarchitecture introduced on February 26, 1999. The brand's initial processors were very similar to the earlier Pentium II-branded microprocessors... )	10
Itanium Itanium Itanium is a family of 64-bit Intel microprocessors that implement the Intel Itanium architecture . Intel markets the processors for enterprise servers and high-performance computing systems...	8	Speculative execution, branch prediction, register renaming, 30 execution units, multithreading
NetBurst (Willamette)	20	Simultaneous multithreading
NetBurst (Northwood)	20	Simultaneous multithreading
NetBurst (Prescott)	31	Simultaneous multithreading
NetBurst (Cedar Mill)	31	Simultaneous multithreading
Core	14
Intel Atom Intel Atom Intel Atom is the brand name for a line of ultra-low-voltage x86 and x86-64 CPUs from Intel, designed in 45 nm CMOS and used mainly in netbooks, nettops, embedded application ranging from health care to advanced robotics and Mobile Internet devices...	16	Simultaneous multithreading, in-order. No instruction reordering, speculative execution, or register renaming.
Nehalem		Simultaneous multithreading, integrated memory controller, L1/L2/L3 cache
Sandy Bridge Sandy Bridge (microarchitecture) Sandy Bridge is the codename for a microarchitecture developed by Intel beginning in 2005 for central processing units in computers to replace the Nehalem microarchitecture...		Simultaneous multithreading, multicore, integrated memory controller, L1/L2/L3 cache. 2 threads per core.
Haswell	14	Multicore
LatticeMico32 LatticeMico32 LatticeMico32 is a 32-bit microprocessor soft core from Lattice Semiconductor optimized for field-programmable gate arrays . It uses a Harvard architecture, which means the instruction and data buses are separate. Bus arbitration logic can be used to combine the two buses, if desired.LatticeMico32...	6	Harvard architecture
POWER1 POWER1 The POWER1 is a multi-chip CPU developed and fabricated by IBM that implemented the POWER instruction set architecture . It was originally known as the “RISC System/6000 CPU” or when an abbreviated form, the “RS/6000 CPU” before introduction of successors required the original name to be replaced...		Supescalar, out-of-order execution
POWER3 POWER3 The POWER3 is a microprocessor, designed and exclusively manufactured by IBM, that implemented the 64-bit version of the PowerPC instruction set architecture , including all of the optional instructions of the ISA such as the POWER2. It was introduced on 5 October 1998, debuting in the RS/6000 43P...		Supescalar, out-of-order execution
POWER4 POWER4 The POWER4 is a microprocessor developed by International Business Machines that implemented the 64-bit PowerPC and PowerPC AS instruction set architectures. Released in 2001, the POWER4 succeeded the POWER3 and RS64 microprocessors, and was used in RS/6000 and AS/400 computers, ending a separate...		Supescalar, speculative execution, out-of-order execution
POWER5 POWER5 The POWER5 is a microprocessor developed and fabricated by IBM. It is an improved version of the highly successful POWER4. The principal improvements are support for simultaneous multithreading and an on-die memory controller...		Simultaneous multithreading, out-of-order execution, integrated memory controller
POWER6 POWER6 The POWER6 is a microprocessor developed by IBM that implemented the Power ISA v.2.03. When it became available in systems in 2007, it succeeded the POWER5+ as IBM's flagship Power microprocessor...		2-way simultaneous multithreading, in-order execution
POWER7 POWER7 POWER7 is a Power Architecture microprocessor released in 2010 that succeeded the POWER6. POWER7 was developed by IBM at several sites including IBM's Rochester, MN; Austin, TX; Essex Junction, Vermont; T. J. Watson Research Center, NY; Bromont, QC and Böblingen, Germany laboratories...		4 SMT threads per core, 12 execution units per core
401PowerPC 401	3
PowerPC 405	5
PowerPC 440	7
PowerPC 470	9	SMP
PowerPC A2 PowerPC A2 The PowerPC A2 is a massively multicore capable and multithreaded 64-bit Power Architecture processor core designed by IBM using the Power ISA v.2.06 specification. Versions of processors based on the A2 core range from a 2.3 GHz version with 16 cores consuming 65 W to a less powerful, four core...	15
PowerPC e300 PowerPC e300 The PowerPC e300 is a family of 32-bit Power Architecture microprocessor cores developed by Freescale for primary use in system-on-a-chip designs with speed ranging up to 800 MHz, thus making them ideal for embedded applications....	4	Superscalar, Branch prediction
PowerPC e500 PowerPC e500 The PowerPC e500 is a 32-bit Power Architecture-based microprocessor core from Freescale Semiconductor. The core is compatible with the older PowerPC Book E specification as well as the Power ISA v.2.03. It has a dual issue, seven-stage pipeline with FPUs , 32/32 KiB data and instruction L1 caches...	Dual 7 stage	Multicore
PowerPC e600 PowerPC e600 The PowerPC e600 is a family of 32-bit Power Architecture microprocessor cores developed by Freescale for primary use in high performance system-on-a-chip designs with speed ranging over 2 GHz, thus making them ideal for high performance routing and telecommunications applications...	3-issue 7 stage	Superscalar out-of-order execution, branch prediction
PowerPC e5500 PowerPC e5500 The PowerPC e5500 is a 64-bit Power Architecture-based microprocessor core from Freescale Semiconductor. The core is compatible with the Power ISA v.2.06 with hypervisor support. It has a four issue, seven-stage out-of-order pipeline with a double precision FPU, three Integer units, 32/32 KB data...	4-issue 7 stage	Out-of-order, multicore
PowerPC 603	4	5 execution units, branch prediction. No SMP.
PowerPC 603q	5	In-order
PowerPC 604	6	Superscalar, out-of-order execution, 6 execution units. SMP support.
PowerPC 620	5	Out-of-order execution- SMP support.
PWRficient PWRficient PWRficient is the name of a series of microprocessors designed by P.A. Semi.PWRficient processors comply with the 64-bit Power Architecture, and are designed for high performance and extreme power efficiency...		Superscalar, out-of-order execution, 6 execution units
R4000 R4000 The R4000 is a microprocessor developed by MIPS Computer Systems that implemented the MIPS III instruction set architecture . Officially announced on 1 October 1991, it was one of the first 64-bit microprocessors and the first MIPS III implementation...	8	Scalar
StrongARM SA-110	5	Scalar, in-order
SuperH SH2	5
SuperH SH2A	5	Superscalar, Harvard architecture
SPARC SPARC SPARC is a RISC instruction set architecture developed by Sun Microsystems and introduced in mid-1987....		Superscalar
HyperSPARC HyperSPARC The hyperSPARC, code-named "Pinnacle", is a microprocessor that implements the SPARC Version 8 instruction set architecture developed by Ross Technology for Cypress Semiconductor....		Superscalar
SuperSPARC SuperSPARC The SuperSPARC is a microprocessor that implements the SPARC V8 instruction set architecture developed by Sun Microsystems. 33 and 40 MHz versions were introduced in 1992. The SuperSPARC contained 3.1 million transistors. It was fabricated by Texas Instruments at Miho, Japan in a 0.8 micrometre...		Superscalar, in-order
SPARC64 VI/VII/VII+		Superscalar, out-of-order
UltraSPARC UltraSPARC The UltraSPARC is a microprocessor developed by Sun Microsystems who is now a part of Oracle Corporation and fabricated by Texas Instruments that implements the SPARC V9 instruction set architecture . It was introduced in mid-1995. It was the first microprocessor from Sun Microsystems to implement...	9
UltraSPARC T1 UltraSPARC T1 \|right\|262px\|UltraSPARC T1 processorSun Microsystems' UltraSPARC T1 microprocessor, known until its 14 November 2005 announcement by its development codename "Niagara", is a multithreading, multicore CPU...	6	Open source, multithreading, multi-core, 4 threads per core, integrated memory controller
UltraSPARC T2 UltraSPARC T2 Sun Microsystems' UltraSPARC T2 microprocessor is a multithreading, multi-core CPU. It is a member of the SPARC family, and the successor to the UltraSPARC T1. The chip is sometimes referred to by its codename, Niagara 2...	8	Open source, multithreading, multi-core, 8 threads per core
SPARC T3		Multithreading, multi-core, 8 threads per core, SMP
SPARC T4 SPARC T4 The SPARC T4 is a SPARC multicore microprocessor introduced in 2011 by Oracle Corporation. The processor is designed to offer high multithreaded performance , as well as high performance single threaded performance from the same chip...		Multithreading, multi-core, 8 threads per core, SMP, out-of-order
VIA C7 VIA C7 The VIA C7 is an x86 central processing unit designed by Centaur Technology and sold by VIA Technologies.- Product history :The C7 delivers a number of improvements to the older VIA C3 cores but is nearly identical to the latest VIA C3 Nehemiah core. The C7 was officially launched in May 2005,...		In-order execution
VIA Nano VIA Nano The VIA Nano is a 64-bit CPU for personal computers. The VIA Nano was released by VIA Technologies in 2008 after five years of development by its CPU division, Centaur Technology... (Isaiah)		Superscalar out-of-order execution, branch prediction, 7 execution units
WinChip WinChip The WinChip series was a low-power Socket 7-based x86 processor designed by Centaur Technology and marketed by its parent company IDT.-Design:The design of the WinChip was quite different from other processors of the time...	4	In-order execution

Bits

Operands

Endianess

Architectures

Microarchitectures

See also