SPARC
Encyclopedia
Sun Microsystems
Sun Microsystems, Inc. was a company that sold :computers, computer components, :computer software, and :information technology services. Sun was founded on February 24, 1982...
and introduced in mid-1987.
SPARC is a registered trademark of SPARC International, Inc.
Incorporation (business)
Incorporation is the forming of a new corporation . The corporation may be a business, a non-profit organisation, sports club, or a government of a new city or town...
, an organization established in 1989 to promote the SPARC architecture, manage SPARC trademarks, and provide conformance testing
Conformance testing
Conformance testing or type testing is testing to determine whether a product or system meets some specified standard that has been developed for efficiency or interoperability....
. Implementations of the original 32-bit
32-bit
The range of integer values that can be stored in 32 bits is 0 through 4,294,967,295. Hence, a processor with 32-bit memory addresses can directly access 4 GB of byte-addressable memory....
SPARC architecture were initially designed and used in Sun's Sun-4
Sun-4
Sun-4 is a series of Unix workstations and servers produced by Sun Microsystems, launched in 1987. The original Sun-4 series were VMEbus-based systems similar to the earlier Sun-3 series, but employing microprocessors based on Sun's own SPARC V7 RISC architecture in place of the 68k family...
workstation and server
Server (computing)
In the context of client-server architecture, a server is a computer program running to serve the requests of other programs, the "clients". Thus, the "server" performs some computational task on behalf of "clients"...
systems, replacing their earlier Sun-3
Sun-3
Sun-3 was the name given to a series of UNIX computer workstations and servers produced by Sun Microsystems, launched on September 9th, 1985. The Sun-3 series were VMEbus-based systems similar to some of the earlier Sun-2 series, but using the Motorola 68020 microprocessor, in combination with the...
systems based on the Motorola 68000 family of processors. Later, SPARC processors were used in SMP
Symmetric multiprocessing
In computing, symmetric multiprocessing involves a multiprocessor computer hardware architecture where two or more identical processors are connected to a single shared main memory and are controlled by a single OS instance. Most common multiprocessor systems today use an SMP architecture...
servers produced by Sun Microsystems
Sun Microsystems
Sun Microsystems, Inc. was a company that sold :computers, computer components, :computer software, and :information technology services. Sun was founded on February 24, 1982...
, Solbourne and Fujitsu
Fujitsu
is a Japanese multinational information technology equipment and services company headquartered in Tokyo, Japan. It is the world's third-largest IT services provider measured by revenues....
, among others, and designed for 64-bit
64-bit
64-bit is a word size that defines certain classes of computer architecture, buses, memory and CPUs, and by extension the software that runs on them. 64-bit CPUs have existed in supercomputers since the 1970s and in RISC-based workstations and servers since the early 1990s...
operation.
SPARC International was intended to open the SPARC architecture to make a larger ecosystem for the design, which has been licensed to several manufacturers, including Texas Instruments
Texas Instruments
Texas Instruments Inc. , widely known as TI, is an American company based in Dallas, Texas, United States, which develops and commercializes semiconductor and computer technology...
, Atmel
Atmel
Atmel Corporation is a manufacturer of semiconductors, founded in 1984. Its focus is on system-level solutions built around flash microcontrollers...
, Cypress Semiconductor
Cypress Semiconductor
Cypress Semiconductor Corporation is a Silicon Valley-based semiconductor design and manufacturing company founded by T. J. Rodgers and others from Advanced Micro Devices. It was formed in 1982 with backing by Sevin Rosen and went public in 1986. The company initially focused on the design and...
, and Fujitsu
Fujitsu
is a Japanese multinational information technology equipment and services company headquartered in Tokyo, Japan. It is the world's third-largest IT services provider measured by revenues....
. As a result of SPARC International, the SPARC architecture is fully open and non-proprietary.
In March 2006, the complete design of Sun Microsystems' UltraSPARC T1 microprocessor was released-in open-source form at OpenSPARC.net and named the OpenSPARC T1. In 2007, the design of Sun's UltraSPARC T2 microprocessor was also released in open-source form, as OpenSPARC T2.
The most recent commercial iterations of the SPARC processor design are the Fujitsu Laboratories Ltd.'s "Venus" 128 GFLOP SPARC64 VIIIfx introduced June 2009, which is used in the 8 petaFLOPS Japanese supercomputer "K computer
K computer
The K computer – named for the Japanese word , which stands for 10 quadrillion – is a supercomputer being produced by Fujitsu at the RIKEN Advanced Institute for Computational Science campus in Kobe, Japan. In June 2011, TOP500 ranked K the world's fastest supercomputer, with a rating...
", and the SPARC T4
SPARC T4
The SPARC T4 is a SPARC multicore microprocessor introduced in 2011 by Oracle Corporation. The processor is designed to offer high multithreaded performance , as well as high performance single threaded performance from the same chip...
introduced by Oracle Corporation
Oracle Corporation
Oracle Corporation is an American multinational computer technology corporation that specializes in developing and marketing hardware systems and enterprise software products – particularly database management systems...
in September 2011; both are 8 core devices running at 2.0GHz, and over 2.5GHz respectively.
Features
The SPARC architecture was heavily influenced by the earlier RISC designs including the RISCBerkeley RISC
Berkeley RISC was one of two seminal research projects into RISC-based microprocessor design taking place under ARPA's VLSI project. RISC was led by David Patterson at the University of California, Berkeley between 1980 and 1984, while the other was taking place only a short drive away at Stanford...
I and II from the University of California, Berkeley
University of California, Berkeley
The University of California, Berkeley , is a teaching and research university established in 1868 and located in Berkeley, California, USA...
and the IBM 801
IBM 801
The 801 was an experimental minicomputer designed by IBM. The resulting architecture was used in various roles in IBM until the 1980s. The 801 was started as a pure research project led by John Cocke in October 1975 at the Thomas J. Watson Research Center. The name 801 comes from the building the...
. These original RISC designs were minimalist, including as few features or op-codes as possible and aiming to execute instructions at a rate of almost one instruction per clock cycle
Clock signal
In electronics and especially synchronous digital circuits, a clock signal is a particular type of signal that oscillates between a high and a low state and is utilized like a metronome to coordinate actions of circuits...
. This made them similar to the MIPS architecture
MIPS architecture
MIPS is a reduced instruction set computer instruction set architecture developed by MIPS Technologies . The early MIPS architectures were 32-bit, and later versions were 64-bit...
in many ways, including the lack of instructions such as multiply or divide. Another feature of SPARC influenced by this early RISC movement is the branch delay slot
Branch delay slot
In computer architecture, a delay slot is an instruction slot that gets executed without the effects of a preceding instruction. The most common form is a single arbitrary instruction located immediately after a branch instruction on a RISC or DSP architecture; this instruction will execute even if...
.
The SPARC processor usually contains as many as 160 general purpose registers
Processor register
In computer architecture, a processor register is a small amount of storage available as part of a CPU or other digital processor. Such registers are addressed by mechanisms other than main memory and can be accessed more quickly...
. At any point, only 32 of them are immediately visible to software - 8 are a set of global registers (one of which, g0, is hard-wired to zero, so only 7 of them are usable as registers) and the other 24 are from the stack
Stack (data structure)
In computer science, a stack is a last in, first out abstract data type and linear data structure. A stack can have any abstract data type as an element, but is characterized by only three fundamental operations: push, pop and stack top. The push operation adds a new item to the top of the stack,...
of registers. These 24 registers form what is called a register window
Register window
In computer engineering, the use of register windows is a technique to improve the performance of a particularly common operation, the procedure call...
, and at function call/return, this window is moved up and down the register stack. Each window has 8 local registers and shares 8 registers with each of the adjacent windows. The shared registers are used for passing function parameters and returning values, and the local registers are used for retaining local values across function calls.
The "Scalable" in SPARC comes from the fact that the SPARC specification allows implementations to scale from embedded processors up through large server processors, all sharing the same core (non-privileged) instruction set. One of the architectural parameters that can scale is the number of implemented register windows; the specification allows from 3 to 32 windows to be implemented, so the implementation can choose to implement all 32 to provide maximum call stack
Call stack
In computer science, a call stack is a stack data structure that stores information about the active subroutines of a computer program. This kind of stack is also known as an execution stack, control stack, run-time stack, or machine stack, and is often shortened to just "the stack"...
efficiency, or to implement only 3 to reduce context switching time, or to implement some number between them. Other architectures that include similar register file
Register file
A register file is an array of processor registers in a central processing unit . Modern integrated circuit-based register files are usually implemented by way of fast static RAMs with multiple ports...
features include Intel i960
Intel i960
Intel's i960 was a RISC-based microprocessor design that became popular during the early 1990s as an embedded microcontroller, becoming a best-selling CPU in that field, along with the competing AMD 29000...
, IA-64, and AMD 29000.
The architecture has gone through several revisions. It gained hardware multiply and divide functionality in Version 8. 64-bit
64-bit
64-bit is a word size that defines certain classes of computer architecture, buses, memory and CPUs, and by extension the software that runs on them. 64-bit CPUs have existed in supercomputers since the 1970s and in RISC-based workstations and servers since the early 1990s...
(addressing and data) were added to the version 9 SPARC specification published in 1994.
In SPARC Version 8, the floating point
Floating point
In computing, floating point describes a method of representing real numbers in a way that can support a wide range of values. Numbers are, in general, represented approximately to a fixed number of significant digits and scaled using an exponent. The base for the scaling is normally 2, 10 or 16...
register file has 16 double precision
Double precision
In computing, double precision is a computer number format that occupies two adjacent storage locations in computer memory. A double-precision number, sometimes simply called a double, may be defined to be an integer, fixed point, or floating point .Modern computers with 32-bit storage locations...
registers. Each of them can be used as two single precision registers, providing a total of 32 single precision registers. An odd-even number pair of double precision registers can be used as a quad precision register, thus allowing 8 quad precision registers. SPARC Version 9 added 16 more double precision registers (which can also be accessed as 8 quad precision registers), but these additional registers can not be accessed as single precision registers.
Tagged add and subtract instructions perform adds and subtracts on values assuming that the bottom two bits do not participate in the computation. This can be useful in the implementation of the run time
Run-time system
A run-time system is a software component designed to support the execution of computer programs written in some computer language...
for ML, Lisp, and similar languages that might use a tagged integer format.
The endianness
Endianness
In computing, the term endian or endianness refers to the ordering of individually addressable sub-components within the representation of a larger data item as stored in external memory . Each sub-component in the representation has a unique degree of significance, like the place value of digits...
of the 32-bit
32-bit
The range of integer values that can be stored in 32 bits is 0 through 4,294,967,295. Hence, a processor with 32-bit memory addresses can directly access 4 GB of byte-addressable memory....
SPARC V8 architecture is purely big-endian. The 64-bit SPARC V9 architecture uses big-endian instructions, but can access data in either big-endian or little-endian byte order, chosen either at the application instruction (load/store) level or at the memory page
Paging
In computer operating systems, paging is one of the memory-management schemes by which a computer can store and retrieve data from secondary storage for use in main memory. In the paging memory-management scheme, the operating system retrieves data from secondary storage in same-size blocks called...
level (via an MMU setting). The latter is often used for accessing data from inherently little-endian devices, such as those on PCI buses.
History
There have been three major revisions of the architecture. The first published revision was the 32-bit SPARC Version 7 (V7) in 1986. SPARC Version 8 (V8), an enhanced SPARC architecture definition, was released in 1990. The main differences between V7 and V8 were the addition of integer multiply and divide instructions, and an upgrade from 80-bit "extended precision" floating-point arithmetic to 128-bit "quad-precisionQuadruple precision floating-point format
In computing, quadruple precision is a binary floating-point computer number format that occupies 16 bytes in computer memory....
" arithmetic. SPARC V8 served as the basis for IEEE Standard 1754-1994, an IEEE standard for a 32-bit microprocessor architecture.
SPARC Version 9, the 64-bit SPARC architecture, was released by SPARC International in 1993. It was developed by the SPARC Architecture Committee consisting of Amdahl Corporation
Amdahl Corporation
Amdahl Corporation is an information technology company which specializes in IBM mainframe-compatible computer products. Founded in 1970 by Dr. Gene Amdahl, a former IBM employee, it has been a wholly owned subsidiary of Fujitsu since 1997...
, Fujitsu
Fujitsu
is a Japanese multinational information technology equipment and services company headquartered in Tokyo, Japan. It is the world's third-largest IT services provider measured by revenues....
, ICL, LSI Logic, Matsushita, Philips
Philips
Koninklijke Philips Electronics N.V. , more commonly known as Philips, is a multinational Dutch electronics company....
, Ross Technology, Sun Microsystems, and Texas Instruments
Texas Instruments
Texas Instruments Inc. , widely known as TI, is an American company based in Dallas, Texas, United States, which develops and commercializes semiconductor and computer technology...
.
In 2002, the SPARC Joint Programming Specification 1 (JPS1) was released by Fujitsu and Sun, describing processor functions which were identically implemented in the CPUs of both companies ("Commonality"). The first CPUs conforming to JPS1 were the UltraSPARC III by Sun and the SPARC64 V by Fujitsu. Functionalities which are not covered by JPS1 are documented for each processor in "Implementation Supplements".
In early 2006, Sun released an extended architecture specification, UltraSPARC Architecture 2005. This includes not only the non-privileged and most of the privileged portions of SPARC V9, but also all the architectural extensions (such as CMT, hyperprivileged, VIS
Visual Instruction Set
Visual Instruction Set, or VIS, is a SIMD instruction set for SPARC V9 microprocessors developed by Sun Microsystems. There are three versions of VIS: VIS 1, VIS 2 and VIS 2+...
1, and VIS 2) present in Sun's UltraSPARC processors starting with the UltraSPARC T1
UltraSPARC T1
|right|262px|UltraSPARC T1 processorSun Microsystems' UltraSPARC T1 microprocessor, known until its 14 November 2005 announcement by its development codename "Niagara", is a multithreading, multicore CPU...
implementation. UltraSPARC Architecture 2005 includes Sun's standard extensions and remains compliant with the full SPARC V9 Level 1 specification.
In 2007, Sun released an updated specification, UltraSPARC Architecture 2007, to which the UltraSPARC T2 implementation complied.
The architecture has provided continuous application binary compatibility from the first SPARC V7 implementation in 1987 into the Sun UltraSPARC Architecture implementations.
Among various implementations of SPARC, Sun's SuperSPARC and UltraSPARC-I were very popular, and were used as reference systems for SPEC
Standard Performance Evaluation Corporation
The Standard Performance Evaluation Corporation is a non-profit organization that aims to "produce, establish, maintain and endorse a standardized set" of performance benchmarks for computers....
CPU95 and CPU2000 benchmarks. The 296 MHz UltraSPARC-II is the reference system for the SPEC CPU2006 benchmark.
The SPARC architecture has been licensed to many companies who have developed and fabricated implementations such as:
- Afara WebsystemsAfara WebsystemsAfara Websystems Inc. was a Sunnyvale, California, USA server company whose goal was to build servers surrounding a custom high-throughput CPU architecture, "developing IP traffic management systems that will bring quality-of-service to the next generation of IP access infrastructure." The word...
- Bipolar Integrated TechnologyBipolar Integrated TechnologyBipolar Integrated Technology was a semiconductor company based in Beaverton, Oregon which sold products implemented with ECL technology. The company was founded in 1983 by former Floating Point Systems, Intel, and Tektronix engineers. The company was later renamed BIT Inc..The initial product...
(BIT) - C-CubeC-CubeC-Cube Microsystems was a pioneer in video compression technology as well as the implementation of that technology into cost-effective semiconductors...
- Cypress SemiconductorCypress SemiconductorCypress Semiconductor Corporation is a Silicon Valley-based semiconductor design and manufacturing company founded by T. J. Rodgers and others from Advanced Micro Devices. It was formed in 1982 with backing by Sevin Rosen and went public in 1986. The company initially focused on the design and...
- ElbrusElbrus (computer)The Elbrus is a line of Soviet and Russian computer systems developed by Lebedev Institute of Precision Mechanics and Computer Engineering.In 1992 a spin-off company Moscow Center of SPARC Technologies was created and continued development....
- FujitsuFujitsuis a Japanese multinational information technology equipment and services company headquartered in Tokyo, Japan. It is the world's third-largest IT services provider measured by revenues....
and Fujitsu Microelectronics - HAL Computer SystemsHAL Computer SystemsHAL Computer Systems, Inc was a Campbell, California-based computer manufacturer founded in 1990 by Andrew Heller, a principal designer of the original IBM POWER architecture...
- HyundaiHyundaiHyundai ) is a global conglomerate company, part of the Korean chaebol, that was founded in South Korea by one of the most famous businessmen in Korean history: Chung Ju-yung...
- LSI Logic
- Magnum SemiconductorMagnum SemiconductorMagnum Semiconductor Inc. is a video compression technology company. The headquarters of the company is in Milpitas, California. The company has an engineering branch at Waterloo, Ontario, Canada....
- Meiko ScientificMeiko ScientificMeiko Scientific Ltd. was a British supercomputer company based in Bristol, founded by members of the design team working on the INMOS transputer microprocessor.-History:...
- Metaflow TechnologiesMetaflow TechnologiesMetaflow Technologies was a La Jolla, CA based microprocessor design company. It was founded in 1988 by Val Popescu, Merle Schultz, Gary Gibson, John Spracklen, and Bruce Lightner....
- Prisma
- Ross Technology
- Parsé Semiconductor Co.Parsé Semiconductor Co.Parsé Semiconductor Co. was established in 2003 in Tehran, Iran, is a digital design house for ASIC, SoC and FPGA designs. The company in 2006 announced it has both designed and produced a 32 bit computer microprocessor inside the country for the first time....
- Scientific Atlanta
- Solbourne ComputerSolbourne ComputerSolbourne Computer Inc. was originally a vendor of computer systems based in Longmont, Colorado, USA, at first 52% owned by Matsushita. In the late 1980s and early '90s, the company produced a range of computer workstations and servers based on the SPARC microprocessor architecture, largely...
- WeitekWeitekWeitek Corporation was a chip-design company that originally concentrated on floating point units for a number of commercial CPU designs. During the early to mid-1980s, Weitek designs could be found powering a number of high-end designs and parallel processing supercomputers...
SPARC microprocessor specifications
This table contains specifications for certain SPARC processors: frequency (megahertz), architecture version, release year, number of threads (threads per core multiplied by the number of cores), fabrication process (micrometers), number of transistors (millions), die size (square millimetres), number of I/OInput/output
In computing, input/output, or I/O, refers to the communication between an information processing system , and the outside world, possibly a human, or another information processing system. Inputs are the signals or data received by the system, and outputs are the signals or data sent from it...
pins, dissipated power (watts), voltage, and cache sizes—data, instruction, L2 and L3 (kibibytes).
| Name (codename) | Model | Frequency (MHz) | Arch. version | Year | Total threads | Process (µm) | Transistors (millions) | Die size (mm²) | IO Pins | Power (W) | Voltage (V) | L1 Dcache (k) | L1 Icache (k) | L2 Cache (k) | L3 Cache (k) |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| SPARC | (various), including MB86900 MB86900 The MB86900 is a microprocessor chip set that implements the SPARC V7 instruction set architecture developed by Sun Microsystems. It was the first implementation of SPARC and was used in the first SPARC-based workstation, the Sun Microsystems Sun-4. The chip set operated at 16.67 MHz. The chip set... |
14.28–40 | V7 | 1987–1992 | 1×1=1 | 0.8–1.3 | ~0.1–1.8 | ||||||||
| 160–256 | |||||||||||||||
| 0–128 (unified) | none | none | |||||||||||||
| microSPARC MicroSPARC The microSPARC is a microprocessor implementing the SPARC V8 instruction set architecture developed by Sun Microsystems. It was a low-end microprocessor intended for low-end workstations and embedded systems. The microprocessor was developed by Sun, but the floating-point unit was licensed from... I (Tsunami) |
TI TMS390S10 | 40–50 | V8 | 1992 | 1×1=1 | 0.8 | 0.8 | 225? | 288 | 2.5 | 5 | 2 | 4 | none | none |
| SuperSPARC SuperSPARC The SuperSPARC is a microprocessor that implements the SPARC V8 instruction set architecture developed by Sun Microsystems. 33 and 40 MHz versions were introduced in 1992. The SuperSPARC contained 3.1 million transistors. It was fabricated by Texas Instruments at Miho, Japan in a 0.8 micrometre... I (Viking) |
TI TMX390Z50 / Sun STP1020 | 33–60 | V8 | 1992 | 1×1=1 | 0.8 | 3.1 | ||||||||
| 293 | 14.3 | 5 | 16 | 20 | 0-2048 | none | |||||||||
| SPARClite | Fujitsu MB8683x | 66–108 | V8E | 1992 | 1×1=1 | ||||||||||
| 144, 176 | |||||||||||||||
| 2.5/3.3V-5.0V, 2.5V-3.3V | 1, 2, 8, 16 | 1, 2, 8, 16 | none | none | |||||||||||
| hyperSPARC HyperSPARC The hyperSPARC, code-named "Pinnacle", is a microprocessor that implements the SPARC Version 8 instruction set architecture developed by Ross Technology for Cypress Semiconductor.... (Colorado 1) |
Ross RT620A | 40–90 | V8 | 1993 | 1×1=1 | 0.5 | 1.5 | ||||||||
| 5? | 0 | 8 | 128-256 | none | |||||||||||
| microSPARC II (Swift) | Fujitsu MB86904 / Sun STP1012 | 60–125 | V8 | 1994 | 1×1=1 | 0.5 | 2.3 | 233 | 321 | 5 | 3.3 | 8 | 16 | none | none |
| hyperSPARC (Colorado 2) | Ross RT620B | 90–125 | V8 | 1994 | 1×1=1 | 0.4 | 1.5 | ||||||||
| 3.3 | 0 | 8 | 128-256 | none | |||||||||||
| SuperSPARC II (Voyager) | Sun STP1021 | 75–90 | V8 | 1994 | 1×1=1 | 0.8 | 3.1 | 299 | |||||||
| 16 | |||||||||||||||
| 16 | 20 | 1024-2048 | none | ||||||||||||
| hyperSPARC (Colorado 3) | Ross RT620C | 125–166 | V8 | 1995 | 1×1=1 | 0.35 | 1.5 | ||||||||
| 3.3 | 0 | 8 | 512-1024 | none | |||||||||||
| TurboSPARC TurboSPARC The TurboSPARC is a microprocessor that implements the SPARC V8 instruction set architecture developed by Fujitsu Microelectronics, Inc. , the United States subsidiary of Fujitsu Limited located in San Jose, California. It was a low-end microprocessor primarily developed as an upgrade for the Sun... |
Fujitsu MB86907 | 160–180 | V8 | 1996 | 1×1=1 | 0.35 | 3.0 | 132 | 416 | 7 | 3.5 | 16 | 16 | 512 | none |
| UltraSPARC UltraSPARC The UltraSPARC is a microprocessor developed by Sun Microsystems who is now a part of Oracle Corporation and fabricated by Texas Instruments that implements the SPARC V9 instruction set architecture . It was introduced in mid-1995. It was the first microprocessor from Sun Microsystems to implement... (Spitfire) |
Sun STP1030 | 143–167 | V9 | 1995 | 1×1=1 | 0.47 | 5.2 | 315 | 521 | 30 | 3.3 | 16 | 16 | 512-1024 | none |
| UltraSPARC (Hornet) | Sun STP1030 | 200 | V9 | 1998 | 1×1=1 | 0.42 | 5.2 | 265 | 521 | ||||||
| 3.3 | 16 | 16 | 512-1024 | none | |||||||||||
| hyperSPARC (Colorado 4) | Ross RT620D | 180–200 | V8 | 1996 | 1×1=1 | 0.35 | 1.7 | ||||||||
| 3.3 | 16 | 16 | 512 | none | |||||||||||
| SPARC64 SPARC64 SPARC64 is a microprocessor developed by HAL Computer Systems and fabricated by Fujitsu. It implements the SPARC V9 instruction set architecture , the first microprocessor to do so. SPARC64 was HAL's first microprocessor and was the first in the SPARC64 brand. It operates at 101 and 118 MHz... |
Fujitsu (HAL) | 101–118 | V9 | 1995 | 1×1=1 | 0.4 | |||||||||
| Multichip | 286 | 50 | 3.8 | 128 | 128 | ||||||||||
| SPARC64 II | Fujitsu (HAL) | 141–161 | V9 | 1996 | 1×1=1 | 0.35 | |||||||||
| Multichip | 286 | 64 | 3.3 | 128 | 128 | ||||||||||
| SPARC64 III | Fujitsu (HAL) MBCS70301 | 250–330 | V9 | 1998 | 1×1=1 | 0.24 | 17.6 | 240 | |||||||
| 2.5 | 64 | 64 | 8192 | ||||||||||||
| UltraSPARC II UltraSPARC II The UltraSPARC II, code-named "Blackbird", is a microprocessor implementation of the SPARC V9 instruction set architecture developed by Sun Microsystems. Marc Tremblay was the chief architect... s (Blackbird) |
Sun STP1031 | 250–400 | V9 | 1997 | 1×1=1 | 0.35 | 5.4 | 149 | 521 | 25 | 2.5 | 16 | 16 | 1024 or 4096 | none |
| UltraSPARC IIs (Sapphire-Black) | Sun STP1032 / STP1034 | 360–480 | V9 | 1999 | 1×1=1 | 0.25 | 5.4 | 126 | 521 | 21 | 1.9 | 16 | 16 | 1024–8192 | none |
| UltraSPARC IIi UltraSPARC III The UltraSPARC III, code-named "Cheetah", is a microprocessor that implements the SPARC V9 instruction set architecture developed by Sun Microsystems and fabricated by Texas Instruments. It was introduced in 2001 and operated at 600 to 900 MHz. It was succeeded by the UltraSPARC IV in 2004... (Sabre) |
Sun SME1040 | 270–360 | V9 | 1997 | 1×1=1 | 0.35 | 5.4 | 156 | 587 | 21 | 1.9 | 16 | 16 | 256–2048 | none |
| UltraSPARC IIi (Sapphire-Red) | Sun SME1430 | 333–480 | V9 | 1998 | 1×1=1 | 0.25 | 5.4 | ||||||||
| 587 | 21 | 1.9 | 16 | 16 | 2048 | none | |||||||||
| UltraSPARC IIe (Hummingbird) | Sun SME1701 | 400–500 | V9 | 1999 | 1×1=1 | 0.18 Al | |||||||||
| 370 | 13 | 1.5-1.7 | 16 | 16 | 256 | none | |||||||||
| UltraSPARC IIi (IIe+) (Phantom) | Sun SME1532 | 550–650 | V9 | 2000 | 1×1=1 | 0.18 Cu | |||||||||
| 370 | 17.6 | 1.7 | 16 | 16 | 512 | none | |||||||||
| SPARC64 GP | Fujitsu SFCB81147 | 400–563 | V9 | 2000 | 1×1=1 | 0.18 | 30.2 | 217 | |||||||
| 1.8 | 128 | 128 | 8192 | ||||||||||||
| SPARC64 GP | -- | 600–810 | V9 | ||||||||||||
| 1×1=1 | 0.15 | 30.2 | |||||||||||||
| 1.5 | 128 | 128 | 8192 | ||||||||||||
| SPARC64 IV | Fujitsu MBCS80523 | 450–810 | V9 | 2000 | 1×1=1 | 0.13 | |||||||||
| 128 | 128 | 2048 | |||||||||||||
| UltraSPARC III UltraSPARC III The UltraSPARC III, code-named "Cheetah", is a microprocessor that implements the SPARC V9 instruction set architecture developed by Sun Microsystems and fabricated by Texas Instruments. It was introduced in 2001 and operated at 600 to 900 MHz. It was succeeded by the UltraSPARC IV in 2004... (Cheetah) |
Sun SME1050 | 600 | V9 / JPS1 | 2001 | 1×1=1 | 0.18 Al | 29 | 330 | 1368 | 53 | 1.6 | 64 | 32 | 8192 | none |
| UltraSPARC III (Cheetah) | Sun SME1052 | 750–900 | V9 / JPS1 | 2001 | 1×1=1 | 0.13 Al | 29 | ||||||||
| 1368 | |||||||||||||||
| 1.6 | 64 | 32 | 8192 | none | |||||||||||
| UltraSPARC III Cu (Cheetah+) | Sun SME1056 | 1002–1200 | V9 / JPS1 | 2001 | 1×1=1 | 0.13 Cu | 29 | 232 | 1368 | 80 | 1.6 | 64 | 32 | 8192 | none |
| UltraSPARC IIIi (Jalapeño) | Sun SME1603 | 1064–1593 | V9 / JPS1 | 2003 | 1×1=1 | 0.13 | 87.5 | 206 | 959 | 52 | 1.3 | 64 | 32 | 1024 | none |
| SPARC64 V SPARC64 V SPARC64 V refers to two unique microprocessors, the SPARC64 V "Zeus" developed by Fujitsu, and an earlier design developed by HAL Computer Systems that never made it into production. The HAL design was canceled in mid-2001 when HAL, a subsidiary of Fujitsu, was closed... (Zeus) |
Fujitsu | 1100–1350 | V9 / JPS1 | 2003 | 1×1=1 | 0.13 | 190 | 289 | 269 | 40 | 1.2 | 128 | 128 | 2048 | |
| SPARC64 V+ (Olympus-B) | Fujitsu | 1650–2160 | V9 / JPS1 | 2004 | 1×1=1 | 0.09 | 400 | 297 | 279 | 65 | 1 | 128 | 128 | 4096 | |
| UltraSPARC IV (Jaguar) | Sun SME1167 | 1050–1350 | V9 / JPS1 | 2004 | 1×2=2 | 0.13 | 66 | 356 | 1368 | 108 | 1.35 | 64 | 32 | 16384 | none |
| UltraSPARC IV+ UltraSPARC IV+ The UltraSPARC IV Jaguar and follow-up UltraSPARC IV+ Panther are microprocessors designed by Sun Microsystems and manufactured by Texas Instruments. They are the fourth generation of UltraSPARC microprocessors, and implement the 64-bit SPARC V9 instruction set architecture... (Panther) |
Sun SME1167A | 1500–2100 | V9 / JPS1 | 2005 | 1×2=2 | 0.09 | 295 | 336 | 1368 | 90 | 1.1 | 64 | 64 | 2048 | 32768 |
| UltraSPARC T1 UltraSPARC T1 |right|262px|UltraSPARC T1 processorSun Microsystems' UltraSPARC T1 microprocessor, known until its 14 November 2005 announcement by its development codename "Niagara", is a multithreading, multicore CPU... (Niagara) |
Sun SME1905 | 1000–1400 | V9 / UA 2005 | 2005 | 4×8=32 | 0.09 | 300 | 340 | 1933 | 72 | 1.3 | 8 | 16 | 3072 | none |
| SPARC64 VI SPARC64 VI The SPARC64 VI, code-named Olympus-C, is a microprocessor, developed by Fujitsu. It implements the SPARC V9 instruction set architecture and is compliant with the Joint Programming Specification developed by Fujitsu and Sun. It is used by Fujitsu and Sun Microsystems in their SPARC Enterprise... (Olympus-C) |
Fujitsu | 2150–2400 | V9 / JPS1 | 2007 | 2×2=4 | 0.09 | 540 | 422 | |||||||
| 120 | |||||||||||||||
| 128x2 | 128x2 | 6144 | none | ||||||||||||
| UltraSPARC T2 UltraSPARC T2 Sun Microsystems' UltraSPARC T2 microprocessor is a multithreading, multi-core CPU. It is a member of the SPARC family, and the successor to the UltraSPARC T1. The chip is sometimes referred to by its codename, Niagara 2... (Niagara 2) |
Sun SME1908A | 1000–1600 | V9 / UA 2007 | 2007 | 8×8=64 | 0.065 | 503 | 342 | 1831 | 95 | 1.1–1.5 | 8 | 16 | 4096 | none |
| UltraSPARC T2 Plus (Victoria Falls) | Sun SME1910A | 1200–1600 | V9 / UA 2007 | 2008 | 8×8=64 | 0.065 | 503 | 342 | 1831 | - | - | 8 | 16 | 4096 | none |
| SPARC64 VII (Jupiter) | Fujitsu | 2400–2880 | V9 / JPS1 | 2008 | 2×4=8 | 0.065 | 600 | 445 | |||||||
| 150 | |||||||||||||||
| 64x4 | 64x4 | 6144 | none | ||||||||||||
| UltraSPARC "RK" (Rock Rock processor Rock was a multithreading, multicore, SPARC microprocessor developed at Sun Microsystems. Now canceled, it was a separate development from the CoolThreads/Niagara family of processors.... ) |
Sun SME1832 | 2300 | V9 / -- | canceled | 2×16=32 | 0.065 | ? | 396 | 2326 | ? | ? | 32 | 32 | 2048 | ? |
| SPARC64 VIIIfx (Venus) | Fujitsu | 2000 | V9 / JPS1 | 2009 | 2x8=16 | 0.045 | 760 | 513 | 1271 | 58 typ | ? | 32x8 | 32x8 | 5120 | none |
| SPARC T3 (Rainbow Falls) | Oracle/Sun | 1650 | V9 / UA _?_ | 2010 | 8×16=128 | 0.040 | ???? | 371 | ? | 139 | ? | 8 | 16 | 6144 | none |
| SPARC64 VII+ (Jupiter-E or M3 ) | Fujitsu | 2667 - 3000 | V9 / JPS1 | 2010 | 2x4=8 | 0.065 | |||||||||
| 160 | |||||||||||||||
| 64x4 | 64x4 | 12288 | none | ||||||||||||
| MCST-4R | MCST (Russia) | 750 - 1000 | V9 | 2010 | 1x4=4 | 0.09 | 150 | 115 | |||||||
| 15 | 1 | 32 | 16 | 2048 | none | ||||||||||
| SPARC T4 SPARC T4 The SPARC T4 is a SPARC multicore microprocessor introduced in 2011 by Oracle Corporation. The processor is designed to offer high multithreaded performance , as well as high performance single threaded performance from the same chip... (Yosemite Falls) |
Oracle | 2850 - 3000 | V9 / OSA2011? | 2011 | 8×8=64 | 0.04 | 855 | 403 | ? | 240 | ? | 16x8 | 16x8 | 128x8 | 4096 |
| Name (codename) | Model | Frequency (MHz) | Arch. version | Year | Total threads | Process (µm) | Transistors (millions) | Die size (mm²) | IO Pins | Power (W) | Voltage (V) | L1 Dcache (k) | L1 Icache (k) | L2 Cache (k) | L3 Cache (k) |
Operating system support
SPARC machines have generally used Sun's SunOSSunOS
SunOS is a version of the Unix operating system developed by Sun Microsystems for their workstation and server computer systems. The SunOS name is usually only used to refer to versions 1.0 to 4.1.4 of SunOS...
, Solaris or OpenSolaris
OpenSolaris
OpenSolaris was an open source computer operating system based on Solaris created by Sun Microsystems. It was also the name of the project initiated by Sun to build a developer and user community around the software...
, but other operating system
Operating system
An operating system is a set of programs that manage computer hardware resources and provide common services for application software. The operating system is the most important type of system software in a computer system...
s such as NeXTSTEP
NEXTSTEP
NeXTSTEP was the object-oriented, multitasking operating system developed by NeXT Computer to run on its range of proprietary workstation computers, such as the NeXTcube...
, RTEMS
RTEMS
RTEMS is a free open source real-time operating system designed for embedded systems....
, FreeBSD
FreeBSD
FreeBSD is a free Unix-like operating system descended from AT&T UNIX via BSD UNIX. Although for legal reasons FreeBSD cannot be called “UNIX”, as the direct descendant of BSD UNIX , FreeBSD’s internals and system APIs are UNIX-compliant...
, OpenBSD
OpenBSD
OpenBSD is a Unix-like computer operating system descended from Berkeley Software Distribution , a Unix derivative developed at the University of California, Berkeley. It was forked from NetBSD by project leader Theo de Raadt in late 1995...
, NetBSD
NetBSD
NetBSD is a freely available open source version of the Berkeley Software Distribution Unix operating system. It was the second open source BSD descendant to be formally released, after 386BSD, and continues to be actively developed. The NetBSD project is primarily focused on high quality design,...
, and Linux
Linux
Linux is a Unix-like computer operating system assembled under the model of free and open source software development and distribution. The defining component of any Linux system is the Linux kernel, an operating system kernel first released October 5, 1991 by Linus Torvalds...
have also been used.
In 1993, Intergraph
Intergraph
Intergraph Corporation is an American software development and services company. It provides enterprise engineering and geospatially powered software to businesses, governments, and organizations around the world. Intergraph operates through two divisions: Process, Power & Marine and Security,...
announced a port of Windows NT
Windows NT
Windows NT is a family of operating systems produced by Microsoft, the first version of which was released in July 1993. It was a powerful high-level-language-based, processor-independent, multiprocessing, multiuser operating system with features comparable to Unix. It was intended to complement...
to the SPARC architecture, but it was later cancelled.
Open source implementations
Three fully open sourceOpen source
The term open source describes practices in production and development that promote access to the end product's source materials. Some consider open source a philosophy, others consider it a pragmatic methodology...
implementations of the SPARC architecture exist:
- LEONLEONLEON is a 32-bit CPU microprocessor core, based on the SPARC-V8 RISC architecture and instruction set. It was originally designed by the European Space Research and Technology Centre , part of the European Space Agency , and after that by Gaisler Research. It is described in synthesizable VHDL...
, a 32-bit, SPARC Version 8 implementation, designed especially for space use. Source codeSource codeIn computer science, source code is text written using the format and syntax of the programming language that it is being written in. Such a language is specially designed to facilitate the work of computer programmers, who specify the actions to be performed by a computer mostly by writing source...
is written in VHDLVHSIC Hardware Description LanguageVHDL is a hardware description language used in electronic design automation to describe digital and mixed-signal systems such as field-programmable gate arrays and integrated circuits.- History :...
, and licensed under the GPLGNU General Public LicenseThe GNU General Public License is the most widely used free software license, originally written by Richard Stallman for the GNU Project....
. - OpenSPARCOpenSPARCOpenSPARC is an open-source hardware project started in December 2005. The initial contribution to the project was Sun Microsystems' register-transfer level Verilog code for a full 64-bit, 32-thread microprocessor, the UltraSPARC T1 processor. On 21 March 2006, Sun released the source code to the...
T1UltraSPARC T1|right|262px|UltraSPARC T1 processorSun Microsystems' UltraSPARC T1 microprocessor, known until its 14 November 2005 announcement by its development codename "Niagara", is a multithreading, multicore CPU...
, released in 2006, a 64-bit, 32-thread implementation conforming to the UltraSPARC Architecture 2005 and to SPARC Version 9 (Level 1). Source code is written in VerilogVerilogIn the semiconductor and electronic design industry, Verilog is a hardware description language used to model electronic systems. Verilog HDL, not to be confused with VHDL , is most commonly used in the design, verification, and implementation of digital logic chips at the register-transfer level...
, and licensed under many licenses. Most OpenSPARC T1 source code is licensed under the GPL. Source based on existent open source projects will continue to be licensed under their current licenses. Binary programs are licensed under a binary software license agreementSoftware license agreementA software license agreement is a contract between the "licensor" and purchaser of the right to use software. The license may define ways under which the copy can be used, in addition to the automatic rights of the buyer including the first sale doctrine and .Many form contracts are only contained...
.- S1S1 CoreS1 Core is an open source hardware microprocessor design developed by Simply RISC. Based on Sun Microsystems' UltraSPARC T1, the S1 Core is licensed under the GNU General Public License, which is the license Sun chose for the OpenSPARC project.The main goal of the project is to keep the S1 Core as...
, a 64-bit Wishbone compliant CPU core based on the OpenSPARC T1 design. It is a single UltraSPARC v9 core capable of 4 way SMT. Like the T1, the source code is licensed under the GPL.
- S1
- OpenSPARC T2UltraSPARC T2Sun Microsystems' UltraSPARC T2 microprocessor is a multithreading, multi-core CPU. It is a member of the SPARC family, and the successor to the UltraSPARC T1. The chip is sometimes referred to by its codename, Niagara 2...
, released in 2008, a 64-bit, 64-thread implementation conforming to the UltraSPARC Architecture 2007 and to SPARC Version 9 (Level 1). Source code is written in Verilog, and licensed under many licenses. Most OpenSPARC T2 source code is licensed under the GPL. Source based on existent open source projects will continue to be licensed under their current licenses. Binary programs are licensed under a binary Software License Agreement.
A fully open source
Open source
The term open source describes practices in production and development that promote access to the end product's source materials. Some consider open source a philosophy, others consider it a pragmatic methodology...
simulator for the SPARC architecture also exists:
- RAMP Gold, a 32-bit, 64-thread SPARC Version 8 implementation, designed for FPGA-based architecture simulation. RAMP Gold is written in ~36,000 lines of SystemverilogSystemVerilogIn the semiconductor and electronic design industry, SystemVerilog is a combined Hardware Description Language and Hardware Verification Language based on extensions to Verilog.-History:...
, and licensed under the BSD licensesBSD licensesBSD licenses are a family of permissive free software licenses. The original license was used for the Berkeley Software Distribution , a Unix-like operating system after which it is named....
.
Supercomputers
As of June 2011, only two supercomputers (#1 and #73) using SPARC microprocessors are included in the world's top 500 fastest supercomputers according to the TOP500TOP500
The TOP500 project ranks and details the 500 most powerful known computer systems in the world. The project was started in 1993 and publishes an updated list of the supercomputers twice a year...
list.
Fujitsu's K computer
K computer
The K computer – named for the Japanese word , which stands for 10 quadrillion – is a supercomputer being produced by Fujitsu at the RIKEN Advanced Institute for Computational Science campus in Kobe, Japan. In June 2011, TOP500 ranked K the world's fastest supercomputer, with a rating...
ranked #1 in Top500 - June 2011 list. It combines 68544 SPARC64 VIIIfx CPUs, each with eight cores, for a total of 548,352 cores—almost twice as many as any other system in the TOP500. The K Computer is more powerful than the next five systems on the list combined, and has the lowest power to performance ratio of any current supercomputer system. It also ranked #6 in Green500 - June 2011 list, with a score of 824.56 MFLOPS/W.
Tianhe-I
Tianhe-I
Tianhe-I, Tianhe-1, or TH-1 , in English, "Milky Way Number One", is a supercomputer capable of an Rmax of 2.566 petaFLOPS...
A (currently #2) has a number of nodes with SPARC processors developed by China (based on OpenSPARC
OpenSPARC
OpenSPARC is an open-source hardware project started in December 2005. The initial contribution to the project was Sun Microsystems' register-transfer level Verilog code for a full 64-bit, 32-thread microprocessor, the UltraSPARC T1 processor. On 21 March 2006, Sun released the source code to the...
). However, those processors did not contribute to the LINPACK
LINPACK
LINPACK is a software library for performing numerical linear algebra on digital computers. It was written in Fortran by Jack Dongarra, Jim Bunch, Cleve Moler, and Gilbert Stewart, and was intended for use on supercomputers in the 1970s and early 1980s...
score.
On Dec. 2, 2010, Oracle unveiled the SPARC SuperCluster with T3-4 Servers, surpassing the HP Integrity Superdome and the IBM Power 780 server, reaching speeds of 30,249,688 tpmC.
See also
- ERC32ERC32ERC32 is a radiation-tolerant 32-bit RISC processor developed for space applications. It was developed by Temic . Two versions have been manufactured, the ERC32 Chip Set , and the ERC32 Single Chip . These implementations follows SPARC V7 specifications...
– based on SPARC V7 specification - OpenSPARCOpenSPARCOpenSPARC is an open-source hardware project started in December 2005. The initial contribution to the project was Sun Microsystems' register-transfer level Verilog code for a full 64-bit, 32-thread microprocessor, the UltraSPARC T1 processor. On 21 March 2006, Sun released the source code to the...
– an open source project based on the UltraSPARC T1 design - Rock processorRock processorRock was a multithreading, multicore, SPARC microprocessor developed at Sun Microsystems. Now canceled, it was a separate development from the CoolThreads/Niagara family of processors....
– A multicore and multithread microprocessor with an emphasis on floating-point performance - Ross Technology, Inc.Ross Technology, Inc.Ross Technology, Inc. was a semiconductor design and manufacturing company, specializing in SPARC microprocessors. It was founded in Austin, Texas in August 1988 by Dr. Roger D. Ross, a leading computer scientist who headed Motorola's Advanced Microprocessor Division and directed the developments...
– A SPARC microprocessor developer during the 1980s and 1990s - Sparcle – modified SPARC with multiprocessing support used by the MIT Alewife project
- UltraSPARC T1UltraSPARC T1|right|262px|UltraSPARC T1 processorSun Microsystems' UltraSPARC T1 microprocessor, known until its 14 November 2005 announcement by its development codename "Niagara", is a multithreading, multicore CPU...
– Sun's first multicore and multithread CPU (code-named "Niagara") - UltraSPARC T2UltraSPARC T2Sun Microsystems' UltraSPARC T2 microprocessor is a multithreading, multi-core CPU. It is a member of the SPARC family, and the successor to the UltraSPARC T1. The chip is sometimes referred to by its codename, Niagara 2...
– The successor to T1 - SPARC T3 – The successor to UltraSPARC T2
- MCST-4R – A Russian quad-core microprocessor based on SPARC V9 specification
External links
- SPARC International, Inc.
- SPARC International list of SPARC processors
- SPARC International Technical Documents
- UltraSPARC Architecture 2005 specification - a SPARC architecture specification extended with CMT, hyperprivileged mode, VIS 1, VIS 2, and so forth for UltraSPARC processors
- UltraSPARC Architecture 2007 specification - an updated SPARC architecture specification for UltraSPARC processors shipping 2007+
- UltraSPARC Processors
- SPARC processor images and descriptions
- The Rough Guide to MBus Modules (SuperSPARC, hyperSPARC)