AVR32
Encyclopedia
The AVR32 is a 32-bit
RISC microprocessor
architecture designed by Atmel
. The microprocessor architecture was designed by a handful of people educated at the Norwegian University of Science and Technology
, including lead designer Øyvind Strøm, PhD and CPU architect Erik Renno, M.Sc in Atmel's Norwegian design center.
Most instructions are executed single-cycle. The multiply–accumulate unit is capable of performing a 32-bit * 16-bit + 48-bit arithmetic operation in two cycles (result latency), with an issue rate of one per cycle.
Any resemblance to the 8-bit AVR is only with respect to the design center (both architectures originated out of Atmel Norway, Trondheim
) and some of the debug-tools.
The AVR32A microarchitecture is targeted at cost-sensitive applications, and so does not provide dedicated hardware registers for shadowing of register file registers, status and return address in interrupt contexts. This saves chip area at the expense of slower interrupt handling. The AVR32B, on the other hand, is targeted at applications where interrupt latency is important, so it implements dedicated registers to hold these values for interrupts, exceptions and supervisor calls.
The AVR32 architecture supports a Java Virtual Machine hardware implementation.
The AVR32 Instruction Set Architecture consists of 16-bit (compact) and 32-bit (extended) instructions, with several specialized instructions not found in architectures like MIPS32
or ARMv5 or ARMv6 ISA. Several U.S. patents are filed for the AVR32 ISA and design platform.
Just like the AVR 8-bit microcontroller
architecture, the AVR32 was designed for extremely efficient code density and performance per clock cycle. Atmel used the independent benchmark consortium EEMBC
to benchmark the architecture with various compilers and consistently outperformed both ARMv5 16-bit (THUMB) code and ARMv5 32-bit (ARM
) code by as much as 50% on code-size and 3X on performance.
Atmel says the "picoPower" AVR32 AT32UC3L consumes less than 0.48 mW/MHz in active mode, which it claims is less power
than any other 32-bit
CPU.
, cache
-based design platform. This "AP7000" implementation of the AVR32B architecture supports SIMD
(single instruction multiple data) DSP
(digital signal processing
) instructions to the RISC instruction-set, in addition to Java hardware acceleration. It includes a Memory Management Unit (MMU) and supports operating systems like Linux
. In early 2009, the rumored AP7200 follow-on processor was held back, with resources going into other chips.
In 2007, Atmel launched the second implementation of the AVR32 architecture: the AVR32 UC3 core. This is designed for microcontroller usage, using on-chip flash memory for program storage and running without an MMU.
The AVR32 UC3 core uses a three-stage pipelined
Harvard architecture specially designed to optimize instruction fetches from on-chip flash memory
. The AVR32 UC3 core implements the AVR32A architecture. It shares the same instruction set architecture (ISA) as its AP7 sibling, but differs by not including the optional SIMD instructions or Java support. Still, it shares over 220 instructions. The ISA features atomic bit manipulation to control on-chip peripherals and general purpose I/Os and fixed point DSP
arithmetic.
Both implementations build on a set of peripheral controllers and bus designs first seen in the AT91SAM
ARM-based platforms. Some peripherals first seen in the AP7000, such as the high speed USB peripheral controller, and standalone DMA controller, appeared later in updated ARM9 platforms and then in the ARM Cortex-M3 based products.
Both AVR32 implementations include a Nexus class 2+ based On-Chip Debug framework build with JTAG
.
The UC3 C, announced at the Electronica 2010 in Munich Germany on November 10, 2010, is the first 32-bit AVR microcontroller with a floating-point unit.
32-bit
The range of integer values that can be stored in 32 bits is 0 through 4,294,967,295. Hence, a processor with 32-bit memory addresses can directly access 4 GB of byte-addressable memory....
RISC microprocessor
Microprocessor
A microprocessor incorporates the functions of a computer's central processing unit on a single integrated circuit, or at most a few integrated circuits. It is a multipurpose, programmable device that accepts digital data as input, processes it according to instructions stored in its memory, and...
architecture designed by Atmel
Atmel
Atmel Corporation is a manufacturer of semiconductors, founded in 1984. Its focus is on system-level solutions built around flash microcontrollers...
. The microprocessor architecture was designed by a handful of people educated at the Norwegian University of Science and Technology
Norwegian University of Science and Technology
The Norwegian University of Science and Technology , commonly known as NTNU, is located in Trondheim. NTNU is the second largest of the eight universities in Norway, and, as its name suggests, has the main national responsibility for higher education in engineering and technology...
, including lead designer Øyvind Strøm, PhD and CPU architect Erik Renno, M.Sc in Atmel's Norwegian design center.
Most instructions are executed single-cycle. The multiply–accumulate unit is capable of performing a 32-bit * 16-bit + 48-bit arithmetic operation in two cycles (result latency), with an issue rate of one per cycle.
Any resemblance to the 8-bit AVR is only with respect to the design center (both architectures originated out of Atmel Norway, Trondheim
Trondheim
Trondheim , historically, Nidaros and Trondhjem, is a city and municipality in Sør-Trøndelag county, Norway. With a population of 173,486, it is the third most populous municipality and city in the country, although the fourth largest metropolitan area. It is the administrative centre of...
) and some of the debug-tools.
Architecture
The AVR32 Architecture consists of several micro-architectures, most notably the AVR32A and AVR32B architectures, which describe fixed additions to the Instruction Set Architecture, configurations of the register file and the use of instruction and data-caches.The AVR32A microarchitecture is targeted at cost-sensitive applications, and so does not provide dedicated hardware registers for shadowing of register file registers, status and return address in interrupt contexts. This saves chip area at the expense of slower interrupt handling. The AVR32B, on the other hand, is targeted at applications where interrupt latency is important, so it implements dedicated registers to hold these values for interrupts, exceptions and supervisor calls.
The AVR32 architecture supports a Java Virtual Machine hardware implementation.
The AVR32 Instruction Set Architecture consists of 16-bit (compact) and 32-bit (extended) instructions, with several specialized instructions not found in architectures like MIPS32
MIPS architecture
MIPS is a reduced instruction set computer instruction set architecture developed by MIPS Technologies . The early MIPS architectures were 32-bit, and later versions were 64-bit...
or ARMv5 or ARMv6 ISA. Several U.S. patents are filed for the AVR32 ISA and design platform.
Just like the AVR 8-bit microcontroller
Atmel AVR
The AVR is a modified Harvard architecture 8-bit RISC single chip microcontroller which was developed by Atmel in 1996. The AVR was one of the first microcontroller families to use on-chip flash memory for program storage, as opposed to one-time programmable ROM, EPROM, or EEPROM used by other...
architecture, the AVR32 was designed for extremely efficient code density and performance per clock cycle. Atmel used the independent benchmark consortium EEMBC
EEMBC
EEMBC, the Embedded Microprocessor Benchmark Consortium, is a non-profit organization formed in 1997 with the aim of developing meaningful performance benchmarks for the hardware and software used in embedded systems...
to benchmark the architecture with various compilers and consistently outperformed both ARMv5 16-bit (THUMB) code and ARMv5 32-bit (ARM
ARM architecture
ARM is a 32-bit reduced instruction set computer instruction set architecture developed by ARM Holdings. It was named the Advanced RISC Machine, and before that, the Acorn RISC Machine. The ARM architecture is the most widely used 32-bit ISA in numbers produced...
) code by as much as 50% on code-size and 3X on performance.
Atmel says the "picoPower" AVR32 AT32UC3L consumes less than 0.48 mW/MHz in active mode, which it claims is less power
Low-power electronics
Low-power electronics means that the consumption of electric power is deliberately low, e.g. notebook processors.- Computing elements :The density and speed of integrated-circuit computing elements have increased exponentially for several decades, following a trend described by Moore's Law...
than any other 32-bit
32-bit
The range of integer values that can be stored in 32 bits is 0 through 4,294,967,295. Hence, a processor with 32-bit memory addresses can directly access 4 GB of byte-addressable memory....
CPU.
Implementations
The AVR32 architecture is solely used in Atmel's own products. Atmel launched in 2006 the first implementation of the AVR32 architecture: the AVR32 AP7 core, a 7-stage pipelinedInstruction pipeline
An instruction pipeline is a technique used in the design of computers and other digital electronic devices to increase their instruction throughput ....
, cache
Cache
In computer engineering, a cache is a component that transparently stores data so that future requests for that data can be served faster. The data that is stored within a cache might be values that have been computed earlier or duplicates of original values that are stored elsewhere...
-based design platform. This "AP7000" implementation of the AVR32B architecture supports SIMD
SIMD
Single instruction, multiple data , is a class of parallel computers in Flynn's taxonomy. It describes computers with multiple processing elements that perform the same operation on multiple data simultaneously...
(single instruction multiple data) DSP
Digital signal processor
A digital signal processor is a specialized microprocessor with an architecture optimized for the fast operational needs of digital signal processing.-Typical characteristics:...
(digital signal processing
Digital signal processing
Digital signal processing is concerned with the representation of discrete time signals by a sequence of numbers or symbols and the processing of these signals. Digital signal processing and analog signal processing are subfields of signal processing...
) instructions to the RISC instruction-set, in addition to Java hardware acceleration. It includes a Memory Management Unit (MMU) and supports operating systems like Linux
Linux
Linux is a Unix-like computer operating system assembled under the model of free and open source software development and distribution. The defining component of any Linux system is the Linux kernel, an operating system kernel first released October 5, 1991 by Linus Torvalds...
. In early 2009, the rumored AP7200 follow-on processor was held back, with resources going into other chips.
In 2007, Atmel launched the second implementation of the AVR32 architecture: the AVR32 UC3 core. This is designed for microcontroller usage, using on-chip flash memory for program storage and running without an MMU.
The AVR32 UC3 core uses a three-stage pipelined
Instruction pipeline
An instruction pipeline is a technique used in the design of computers and other digital electronic devices to increase their instruction throughput ....
Harvard architecture specially designed to optimize instruction fetches from on-chip flash memory
Flash memory
Flash memory is a non-volatile computer storage chip that can be electrically erased and reprogrammed. It was developed from EEPROM and must be erased in fairly large blocks before these can be rewritten with new data...
. The AVR32 UC3 core implements the AVR32A architecture. It shares the same instruction set architecture (ISA) as its AP7 sibling, but differs by not including the optional SIMD instructions or Java support. Still, it shares over 220 instructions. The ISA features atomic bit manipulation to control on-chip peripherals and general purpose I/Os and fixed point DSP
Digital signal processor
A digital signal processor is a specialized microprocessor with an architecture optimized for the fast operational needs of digital signal processing.-Typical characteristics:...
arithmetic.
Both implementations build on a set of peripheral controllers and bus designs first seen in the AT91SAM
AT91SAM
AT91SAM are a family of Atmel chips based on the 32-bit RISC microprocessors from ARM. Some are targeted as applications processors, with external memory busses used to access RAM and flash, and large sets of integrated peripherals...
ARM-based platforms. Some peripherals first seen in the AP7000, such as the high speed USB peripheral controller, and standalone DMA controller, appeared later in updated ARM9 platforms and then in the ARM Cortex-M3 based products.
Both AVR32 implementations include a Nexus class 2+ based On-Chip Debug framework build with JTAG
JTAG
Joint Test Action Group is the common name for what was later standardized as the IEEE 1149.1 Standard Test Access Port and Boundary-Scan Architecture. It was initially devised for testing printed circuit boards using boundary scan and is still widely used for this application.Today JTAG is also...
.
The UC3 C, announced at the Electronica 2010 in Munich Germany on November 10, 2010, is the first 32-bit AVR microcontroller with a floating-point unit.
AP7 Core
UC3 Core
- UC3A0/1 Series - devices deliver 91 DhrystoneDhrystoneDhrystone is a synthetic computing benchmark program developed in 1984 by Reinhold P. Weicker intended to be representative of system programming. The Dhrystone grew to become representative of general processor performance...
MIPS (DMIPS) at 66 MHz (1 flash wait-state) and consume 40 mA @66 MHz at 3.3V.
- UC3A3256/128/64 Series - devices deliver 91 DhrystoneDhrystoneDhrystone is a synthetic computing benchmark program developed in 1984 by Reinhold P. Weicker intended to be representative of system programming. The Dhrystone grew to become representative of general processor performance...
MIPS (DMIPS) at 66 MHz and consume 40 mA @66 MHz at 3.3V.
- UC3B Series - deliver 72 Dhrystone MIPS (DMIPS) at 60 MHz and consume 23 mA @66 MHz at 3.3V.
- UC3L064/32/16 - deliver 64 Dhrystone MIPS (DMIPS) at 50 MHz and consume 15 mA @50 MHz at 1.8V.
Boards
- AT32AP7000 development environment (STK1000)
- AT32AP7000 Network Gateway Kit (NGW100)
- AT32AP7000 board with FPGA, video decoder and Power over Ethernet (Hammerhead)
- AT32AP7000 Indefia Embedded Linux Board with ZigBee support
- All AT32UC3 Series Generic Evaluation platform (STK600)
- AT32UC3A0/1 Series Evaluation Kit (EVK1100)
- AT32UC3A0/1 Series Audio Evaluation Kit (EVK1105)
- AT32UC3A3 Series Evaluation Kit (EVK1104)
- AT32UC3B Series Evaluation Kit (EVK1101)
- AT32UC3B Breadboard module (Copper)
External links
- Atmel AVR32
- AVR32 Linux Project contains recent Linux kernel patches and GCCGNU Compiler CollectionThe GNU Compiler Collection is a compiler system produced by the GNU Project supporting various programming languages. GCC is a key component of the GNU toolchain...
/ binutils - AVR Freaks The AVR Freaks AVR32 Forums
- FreeRTOS.org Free real time kernel for AVR32 flash micros
- OpenEmbedded supports cross-compilation for thousands of packages for the AVR32
- KaeilOS open source build-system supporting the cross compilation for the AVR32
- T2 SDE A build-system supporting the cross compilation to AVR32
- embOS for AVR32 Operating System port for AVR32
- Micrium µC/OS-II Operating System port for AVR32
- ThreadX RTOS for AVR32
- Debian AVR32 port
- eHalOS eHalOS is a small open source AVR32 multiprocessing OS
- uTasker project for the AVR32 UC3A with AVR32 simulator - free for non-commercial use and fully supported