SPARC T4
Encyclopedia
The SPARC T4 is a SPARC
SPARC
SPARC is a RISC instruction set architecture developed by Sun Microsystems and introduced in mid-1987....

 multicore microprocessor introduced in 2011 by Oracle Corporation
Oracle Corporation
Oracle Corporation is an American multinational computer technology corporation that specializes in developing and marketing hardware systems and enterprise software products – particularly database management systems...

. The processor is designed to offer high multithreaded performance (8 threads per core, 8 cores per chip), as well as high performance single threaded performance from the same chip. The chip is the first Sun/Oracle SPARC chip to use out-of-order integer execution units, and also incorporates one floating point unit and a one dedicated cryptographic unit per core. The cores use the 64-bit, SPARC version 9 architecture, running at frequencies between 2.85 and 3.0 GHz, and are built at a 40nm process size with total chip die size of 403mm2.

History and design

A 8 core, 8 thread per core chip built at a 40nm process, and running at 2.5GHz was described in Sun Microsystems
Sun Microsystems
Sun Microsystems, Inc. was a company that sold :computers, computer components, :computer software, and :information technology services. Sun was founded on February 24, 1982...

 processor roadmap of 2009, codenamed Yosemite Falls, and given an expected release date of late 2011, and was expected to introduce a new microarchitecture, codenamed "VT Core"; the online technology website The Register
The Register
The Register is a British technology news and opinion website. It was founded by John Lettice, Mike Magee and Ross Alderson in 1994 as a newsletter called "Chip Connection", initially as an email service...

 speculated that this chip would be named "T4" , being the successor to the SPARC T3. The Yosemite Falls CPU product remained on Oracle Corporation
Oracle Corporation
Oracle Corporation is an American multinational computer technology corporation that specializes in developing and marketing hardware systems and enterprise software products – particularly database management systems...

's processor roadmap after the company took over Sun in early 2010. In December 2010 the T4 processor was confirmed by Oracle's VP of hardware development to be designed for improved per-thread performance, with 8 cores, with an expected release within 1 year.

The processor design was presented at the 2011 Hot Chips
Hot Chips
Hot Chips is an IEEE sponsored technological symposium which is held every year in August on Stanford University campus since 1989. The general emphasis of the conference are microprocessors and integrated circuits. Processor makers often announce details about future processor designs at the...

 conference, the cores (renamed "S3" from "VT") included a dual issue 16 stage integer pipeline
Instruction pipeline
An instruction pipeline is a technique used in the design of computers and other digital electronic devices to increase their instruction throughput ....

, and 11-cycle floating point
Floating point
In computing, floating point describes a method of representing real numbers in a way that can support a wide range of values. Numbers are, in general, represented approximately to a fixed number of significant digits and scaled using an exponent. The base for the scaling is normally 2, 10 or 16...

 pipeline, both giving improvements over the previous ("S2") core used in the SPARC T3 processor. Each core had associated 16KB data and 16KB instruction L1 caches, and 128KB L2 Cache. Cores also include a thread priority mechanism (called "critical thread API") whereby one thread gains preferential access to a core's hardware giving increased performance. Cryptographic performance was also increased by design improvements over the T3 chip. All eight cores share 4MB L3 Cache. Total transistor count was approximately 855 million.

The SPARC T4 processor was officially introduced as part of Oracle's T4 server product in September 2011; the design was the first Sun/Oracle SPARC processor with out-of-order execution
Out-of-order execution
In computer engineering, out-of-order execution is a paradigm used in most high-performance microprocessors to make use of instruction cycles that would otherwise be wasted by a certain type of costly delay...

. Initial product releases of a single T4 processor rack server ran at 2.85GHz, processor speeds of up to 3GHz were achieved on the early systems.
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