Transmeta Crusoe
Encyclopedia
The Crusoe is a family of x86-compatible microprocessor
s developed by Transmeta
. Crusoe was notable for its method of achieving x86 compatibility. Instead of the instruction set architecture being implemented in hardware, or translated by specialized hardware, the Crusoe runs a software abstraction layer, or a virtual machine
, known as the Code Morphing Software
(CMS). The CMS translates machine code
instructions received from programs into native instructions for the microprocessor. In this way, the Crusoe can emulate other instruction set architectures (ISAs).
Currently, this is used to allow the microprocessors to emulate the Intel x86 instruction set. In theory, it is possible for the CMS to be modified to emulate other ISAs. Transmeta demonstrated Crusoe executing Java bytecode by translating the bytecodes into instructions in its native instruction set. The addition of an abstraction layer between the x86 instruction stream and the hardware means that the hardware architecture can change without breaking compatibility, just by modifying the CMS. For example, Efficeon
— a second-generation Transmeta design — has a 256-bit-wide VLIW core versus the 128-bit core of the Crusoe.
Crusoe performs in software some of the functionality traditionally implemented in hardware (e.g. instruction re-ordering), resulting in simpler hardware with fewer transistor
s. The relative simplicity of the hardware means that Crusoe consumes less power (and therefore generates less heat) than other x86-compatible microprocessors running at the same frequency.
The TM3200 operated at clock frequencies of 333-400 MHz. It has a 64 KB instruction cache, a 32 KB data cache and no L2 cache. The TM3200 has an integrated memory controller
supports only SDRAM
and a PCI interface. It measures 77 mm² and uses a 1.5 V power supply, dissipating less than 1.5 W of power (typical).
The TM5400 operated at clock frequencies of 500-800 MHz. Unlike the TM3200, the TM5400 has LongRun power reduction technology. It has a 64 KB instruction cache, a 64 KB data cache and a 256 KB unified L2 cache. The integrated memory controller supports both SDRAM and DDR SDRAM. It also has a PCI interface. It measures 73 mm² and uses a 1.10 V 1.6f V power supply, dissipating 0.5-1.5 W typically and a maximum of 6 W.
As Transmeta was a fabless semiconductor company, that is, they did not have the facilities to fabricate their designs, both were fabricated by IBM Microelectronics, the semiconductor business of International Business Machines (IBM). IBM fabricated the Crusoe in a 0.18 µm CMOS process with five levels of copper interconnect.
The Crusoe is a VLIW microprocessor that executes bundles of instructions, termed molecules by Transmeta. Each molecule contains multiple instructions, termed atoms. The Code Morphing Software translates x86 instructions into native instructions. The native instructions are 32 bits long. Instructions that meet a set of conditions can be executed simultaneously and are combined to form a 64- or 128-bit molecule containing two or four atoms, respectively. In the event that there are not enough instructions to fill a molecule, the software inserts NOP
s as padding to fill out empty slots. This is required in all VLIW architectures and is criticised for being inefficient, which is why there are molecules of two separate lengths.
Transmeta Crusoe, new generation processor provide variable operating modes. Due to dynamic core they vary voltage and frequency dynamically under dynamic load.
Frequency range and dynamic voltage provides for 300 MHz-1.20 V, 400 MHz-1.23 V, 500 MHz-1.35 V,600 MHz-1.53 V,700 MHz-1.75 V, 800 MHz-2.00 V, 900 MHz-2.35, 1000 MHz- 2.80 V. They can vary these ranges depending upon the load. For optimum or minimum load the respective frequencies and voltages get changed.
Microprocessor
A microprocessor incorporates the functions of a computer's central processing unit on a single integrated circuit, or at most a few integrated circuits. It is a multipurpose, programmable device that accepts digital data as input, processes it according to instructions stored in its memory, and...
s developed by Transmeta
Transmeta
Transmeta Corporation was a US-based corporation that licensed low power semiconductor intellectual property. Transmeta originally produced very long instruction word code morphing microprocessors, with a focus on reducing power consumption in electronic devices. It was founded in 1995 by Bob...
. Crusoe was notable for its method of achieving x86 compatibility. Instead of the instruction set architecture being implemented in hardware, or translated by specialized hardware, the Crusoe runs a software abstraction layer, or a virtual machine
Virtual machine
A virtual machine is a "completely isolated guest operating system installation within a normal host operating system". Modern virtual machines are implemented with either software emulation or hardware virtualization or both together.-VM Definitions:A virtual machine is a software...
, known as the Code Morphing Software
Code Morphing Software
Code Morphing Software is the technology used by Transmeta microprocessors to execute x86 instructions. In broad view, CMS reads x86 instructions and generates instructions for a proprietary VLIW processor, in the style of Shade...
(CMS). The CMS translates machine code
Machine code
Machine code or machine language is a system of impartible instructions executed directly by a computer's central processing unit. Each instruction performs a very specific task, typically either an operation on a unit of data Machine code or machine language is a system of impartible instructions...
instructions received from programs into native instructions for the microprocessor. In this way, the Crusoe can emulate other instruction set architectures (ISAs).
Currently, this is used to allow the microprocessors to emulate the Intel x86 instruction set. In theory, it is possible for the CMS to be modified to emulate other ISAs. Transmeta demonstrated Crusoe executing Java bytecode by translating the bytecodes into instructions in its native instruction set. The addition of an abstraction layer between the x86 instruction stream and the hardware means that the hardware architecture can change without breaking compatibility, just by modifying the CMS. For example, Efficeon
Efficeon
The Efficeon processor is Transmeta's second-generation 256-bit VLIW design which employs a software engine to convert code written for x86 processors to the native instruction set of the chip...
— a second-generation Transmeta design — has a 256-bit-wide VLIW core versus the 128-bit core of the Crusoe.
Crusoe performs in software some of the functionality traditionally implemented in hardware (e.g. instruction re-ordering), resulting in simpler hardware with fewer transistor
Transistor
A transistor is a semiconductor device used to amplify and switch electronic signals and power. It is composed of a semiconductor material with at least three terminals for connection to an external circuit. A voltage or current applied to one pair of the transistor's terminals changes the current...
s. The relative simplicity of the hardware means that Crusoe consumes less power (and therefore generates less heat) than other x86-compatible microprocessors running at the same frequency.
Description
The Crusoe was available in two cores: the TM3200 for embedded applications and the TM5400 for low-power personal computing. Both were based on the same architecture but differed in clock frequency and peripheral support.The TM3200 operated at clock frequencies of 333-400 MHz. It has a 64 KB instruction cache, a 32 KB data cache and no L2 cache. The TM3200 has an integrated memory controller
Memory controller
The memory controller is a digital circuit which manages the flow of data going to and from the main memory. It can be a separate chip or integrated into another chip, such as on the die of a microprocessor...
supports only SDRAM
SDRAM
Synchronous dynamic random access memory is dynamic random access memory that is synchronized with the system bus. Classic DRAM has an asynchronous interface, which means that it responds as quickly as possible to changes in control inputs...
and a PCI interface. It measures 77 mm² and uses a 1.5 V power supply, dissipating less than 1.5 W of power (typical).
The TM5400 operated at clock frequencies of 500-800 MHz. Unlike the TM3200, the TM5400 has LongRun power reduction technology. It has a 64 KB instruction cache, a 64 KB data cache and a 256 KB unified L2 cache. The integrated memory controller supports both SDRAM and DDR SDRAM. It also has a PCI interface. It measures 73 mm² and uses a 1.10 V 1.6f V power supply, dissipating 0.5-1.5 W typically and a maximum of 6 W.
As Transmeta was a fabless semiconductor company, that is, they did not have the facilities to fabricate their designs, both were fabricated by IBM Microelectronics, the semiconductor business of International Business Machines (IBM). IBM fabricated the Crusoe in a 0.18 µm CMOS process with five levels of copper interconnect.
The Crusoe is a VLIW microprocessor that executes bundles of instructions, termed molecules by Transmeta. Each molecule contains multiple instructions, termed atoms. The Code Morphing Software translates x86 instructions into native instructions. The native instructions are 32 bits long. Instructions that meet a set of conditions can be executed simultaneously and are combined to form a 64- or 128-bit molecule containing two or four atoms, respectively. In the event that there are not enough instructions to fill a molecule, the software inserts NOP
NOP
In computer science, NOP or NOOP is an assembly language instruction, sequence of programming language statements, or computer protocol command that effectively does nothing at all....
s as padding to fill out empty slots. This is required in all VLIW architectures and is criticised for being inefficient, which is why there are molecules of two separate lengths.
Transmeta Crusoe, new generation processor provide variable operating modes. Due to dynamic core they vary voltage and frequency dynamically under dynamic load.
Frequency range and dynamic voltage provides for 300 MHz-1.20 V, 400 MHz-1.23 V, 500 MHz-1.35 V,600 MHz-1.53 V,700 MHz-1.75 V, 800 MHz-2.00 V, 900 MHz-2.35, 1000 MHz- 2.80 V. They can vary these ranges depending upon the load. For optimum or minimum load the respective frequencies and voltages get changed.
Products
- Casio MPC-701 Pen Tablet PC
- Compaq TC1000Compaq TC1000The TC1000 is a hybrid Tablet PC designed by Compaq, before it was purchased by HP. It used the Transmeta Crusoe processor. Unlike many Tablet PCs which can only operate either in traditional laptop configuration, or with the keyboard folded behind the screen, the display is fully detachable from...
- Compaq T5300, T5500, T5510, T5515, T5700 and T5710 Thin Clients
- ECS EZ-Tablet EZ30
- Flybook
- Fujitsu LifeBook P1032, P1100, P1120, P2110, P2120
- Gateway Touch PadGateway Touch PadThe Gateway Touch Pad was an Internet appliance released on November 10, 2000 at a price of USD599.The Touch Pad was built with a chassis around a 10-inch LCD display with a touch screen for input and controlling basic functions...
- HP Compaq t5300 Thin Client (with TM5600 533 MHz)
- HP Compaq t5500 Thin Client (with TM5800 733 MHz)
- HP Compaq t5700 Thin Client (with TM5800 733 MHz or 1 GHz)
- NEC PowerMate Eco
- NEC Versa DayLite/UltraLite
- PCChips A530 Series Notebook
- Sharp Actius/Mebius MM10
- Sony VAIO PCG-U1 and PCG-U3
- Sony VAIO PCG-C1VP, PCG-C1VPK and PCG-C1VN
- TDV Vison V800XPT Tablet
- Toshiba Libretto L1, L2, L3, L3 Adidas Edition and L5(L1-L3 at 600Mhz and L5 at 800Mhz)
- OQO Model 01 and 01+
- Fujitsu / Siemens Futro S300 (800Mhz TM5800)