P6 (microarchitecture)
Encyclopedia
The P6 microarchitecture is the sixth generation Intel x86 microarchitecture
, implemented by the Pentium Pro
microprocessor that was introduced in November 1995. It is sometimes referred to as i686. It was succeeded by the NetBurst microarchitecture in 2000, but eventually revived in the Pentium M
line of microprocessors. The successor to the Pentium M variant of the P6 microarchitecture is the Core microarchitecture.
CPU in 1995, the immediate successor to the original Pentium design (P5).
Some techniques first used in the x86 space in the P6 core include:
The P6 architecture lasted three generations from the Pentium Pro to Pentium III, and was widely known for low power consumption, excellent integer performance, and relatively high instructions per cycle (IPC). When the new NetBurst (P68) architecture was conceived, initially in the Willamette core, which had relatively low IPC and less efficient overall design both in terms of power consumption and throughput efficiency, the P6 line of processing cores were largely thought to be abandoned.
Realizing their new microarchitecture wasn't the best choice for the mobile space, Intel went back to the drawing board for a design that would be optimally suited for this market segment. The result was a hybrid, and at the time, modernized P6 design called the Pentium M
:
Design Overview
The Pentium M was the most power efficient x86 processor for notebooks for several years, consuming a maximum of 27 watts at maximum load and 4-5 watts while idle. The processing efficiency gains brought about by its modernization allowed it to rival the Mobile Pentium 4 clocked over 1 GHz higher (the fastest-clocked Mobile Pentium 4 compared to the fastest-clocked Pentium M) and equipped with much more memory and bus bandwidth.
brand. Single and dual-core mobile version were sold under the Core Solo, Core Duo, and Pentium Dual-Core brands, and a server version was released as Xeon LV. These processors provided partial solutions to some of the foregoing Pentium M
's shortcomings, by adding to its P6 microarchitecture
:
This resulted in the interim microarchitecture for low-voltage only CPUs, part way between P6 and the following Core microarchitecture.
, Pentium
and Celeron
brand names. The Core microarchitecture is Intel's final mainstream processor line to use FSB
, with all later Intel processors based on Nehalem and following Intel microarchitectures exclusively using the QPI or DMI bus. Improvements from the Intel Core processors were:
While all these chips are technically derivatives of the Pentium Pro the architecture has gone through several radical changes since its inception.
Microarchitecture
In computer engineering, microarchitecture , also called computer organization, is the way a given instruction set architecture is implemented on a processor. A given ISA may be implemented with different microarchitectures. Implementations might vary due to different goals of a given design or...
, implemented by the Pentium Pro
Pentium Pro
The Pentium Pro is a sixth-generation x86 microprocessor developed and manufactured by Intel introduced in November 1, 1995 . It introduced the P6 microarchitecture and was originally intended to replace the original Pentium in a full range of applications...
microprocessor that was introduced in November 1995. It is sometimes referred to as i686. It was succeeded by the NetBurst microarchitecture in 2000, but eventually revived in the Pentium M
Pentium M
The Pentium M brand refers to a family of mobile single-core x86 microprocessors introduced in March 2003 , and forming a part of the Intel Carmel notebook platform under the then new Centrino brand...
line of microprocessors. The successor to the Pentium M variant of the P6 microarchitecture is the Core microarchitecture.
From Pentium Pro to Pentium III
The P6 core was the sixth generation Intel microprocessor in the x86 space. The first implementation of the P6 core was the Pentium ProPentium Pro
The Pentium Pro is a sixth-generation x86 microprocessor developed and manufactured by Intel introduced in November 1, 1995 . It introduced the P6 microarchitecture and was originally intended to replace the original Pentium in a full range of applications...
CPU in 1995, the immediate successor to the original Pentium design (P5).
Some techniques first used in the x86 space in the P6 core include:
- Speculative executionSpeculative executionSpeculative execution in computer systems is doing work, the result of which may not be needed. This performance optimization technique is used in pipelined processors and other systems.-Main idea:...
and out-of-order completionOut-of-order executionIn computer engineering, out-of-order execution is a paradigm used in most high-performance microprocessors to make use of instruction cycles that would otherwise be wasted by a certain type of costly delay...
(called "dynamic execution" by Intel), which required new retire units in the execution core. This lessened pipeline stalls, and in part enabled greater speed-scaling of the Pentium Pro and successive generations of CPUs. - Superpipelining, which increased from Pentium's 5-stage pipeline to 14 of the Pentium Pro, and eventually morphed into the 10-stage pipeline of the Pentium IIIPentium IIIThe Pentium III brand refers to Intel's 32-bit x86 desktop and mobile microprocessors based on the sixth-generation P6 microarchitecture introduced on February 26, 1999. The brand's initial processors were very similar to the earlier Pentium II-branded microprocessors...
, and the 12- to 14-stage pipeline of the Pentium M. - PAEPhysical Address ExtensionIn computing, Physical Address Extension is a feature to allow x86 processors to access a physical address space larger than 4 gigabytes....
and wider 36-bit address bus to support 64 GB of physical memory (the linear address space of a process was still limited to 4 GB). - Register renamingRegister renamingIn computer architecture, register renaming refers to a technique used to avoid unnecessary serialization of program operations imposed by the reuse of registers by those operations.-Problem definition:...
, which enabled more efficient execution of multiple instructions in the pipeline. - CMOV instructionsX86 instruction listingsThe x86 instruction set has been extended several times, introducing wider registers and datatypes and/or new functionality.-x86 integer instructions:...
heavily used in compiler optimizationCompiler optimizationCompiler optimization is the process of tuning the output of a compiler to minimize or maximize some attributes of an executable computer program. The most common requirement is to minimize the time taken to execute a program; a less common one is to minimize the amount of memory occupied...
.
The P6 architecture lasted three generations from the Pentium Pro to Pentium III, and was widely known for low power consumption, excellent integer performance, and relatively high instructions per cycle (IPC). When the new NetBurst (P68) architecture was conceived, initially in the Willamette core, which had relatively low IPC and less efficient overall design both in terms of power consumption and throughput efficiency, the P6 line of processing cores were largely thought to be abandoned.
Revived microarchitecture in Pentium M (Banias and Dothan)
Upon release of the Pentium 4-M and Mobile Pentium 4, it was quickly realized that the new mobile NetBurst processors were not ideal for mobile computing. The Netburst-based processors were simply not as efficient per clock or per watt compared to their P6 predecessors. Mobile Pentium 4 processors ran much hotter than Pentium III-M processors and didn't offer significant performance advantages. Its inefficiency affected not only the cooling system complexity, but also the all-important battery life.Realizing their new microarchitecture wasn't the best choice for the mobile space, Intel went back to the drawing board for a design that would be optimally suited for this market segment. The result was a hybrid, and at the time, modernized P6 design called the Pentium M
Pentium M
The Pentium M brand refers to a family of mobile single-core x86 microprocessors introduced in March 2003 , and forming a part of the Intel Carmel notebook platform under the then new Centrino brand...
:
Design Overview
- Quad-pumped Front Side Bus. With the initial Banias core, Intel adopted the 400 MHz FSB first used in the Pentium 4. The Dothan core moved to the 533 MHz FSB, following the Pentium 4's evolution.
- Larger L2 cacheCPU cacheA CPU cache is a cache used by the central processing unit of a computer to reduce the average time to access memory. The cache is a smaller, faster memory which stores copies of the data from the most frequently used main memory locations...
. Initially 1 MB in the Banias core, then 2 MB in the Dothan core. Dynamic cache activation by quadrant selector from sleep states. - SSE2SSE2SSE2, Streaming SIMD Extensions 2, is one of the Intel SIMD processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2001. It extends the earlier SSE instruction set, and is intended to fully supplant MMX. Intel extended SSE2 to create SSE3...
Streaming SIMD (Single Instruction, Multiple Data) Extensions 2 support. - A 12-14-stage instruction pipeline to achieve higher clock speeds than the Pentium III-M.
- Dedicated register stack management.
- Addition of global history to branch prediction table.
- Micro-ops Fusion of certain sub-instructions mediated by decoding units. x86 commands can be combined into fewer RISC micro operations.
The Pentium M was the most power efficient x86 processor for notebooks for several years, consuming a maximum of 27 watts at maximum load and 4-5 watts while idle. The processing efficiency gains brought about by its modernization allowed it to rival the Mobile Pentium 4 clocked over 1 GHz higher (the fastest-clocked Mobile Pentium 4 compared to the fastest-clocked Pentium M) and equipped with much more memory and bus bandwidth.
Intel Core (Yonah)
The Yonah CPU was launched in January 2006 under the CoreIntel Core
Yonah was the code name for Intel's first generation of 65 nm process mobile microprocessors, based on the Banias/Dothan-core Pentium M microarchitecture. SIMD performance has been improved through the addition of SSE3 instructions and improvements to SSE and SSE2 implementations, while integer...
brand. Single and dual-core mobile version were sold under the Core Solo, Core Duo, and Pentium Dual-Core brands, and a server version was released as Xeon LV. These processors provided partial solutions to some of the foregoing Pentium M
Pentium M
The Pentium M brand refers to a family of mobile single-core x86 microprocessors introduced in March 2003 , and forming a part of the Intel Carmel notebook platform under the then new Centrino brand...
's shortcomings, by adding to its P6 microarchitecture
Microarchitecture
In computer engineering, microarchitecture , also called computer organization, is the way a given instruction set architecture is implemented on a processor. A given ISA may be implemented with different microarchitectures. Implementations might vary due to different goals of a given design or...
:
- SSE3 Support
- Single- and dual-core technology with 2 MB of shared L2 cache (restructuring processor organization)
- Increased FSB speed, with the FSB running at 533 MHz or 667 MHz.
- A 12-stage instruction pipeline.
This resulted in the interim microarchitecture for low-voltage only CPUs, part way between P6 and the following Core microarchitecture.
Successor
On July 27, 2006, the Core microarchitecture, a distant relative of P6, was launched in form of the Core 2 processor. Subsequently, more processors were released with the Core microarchitecture under Core 2, XeonXeon
The Xeon is a brand of multiprocessing- or multi-socket-capable x86 microprocessors from Intel Corporation targeted at the non-consumer server, workstation and embedded system markets.-Overview:...
, Pentium
Pentium
The original Pentium microprocessor was introduced on March 22, 1993. Its microarchitecture, deemed P5, was Intel's fifth-generation and first superscalar x86 microarchitecture. As a direct extension of the 80486 architecture, it included dual integer pipelines, a faster FPU, wider data bus,...
and Celeron
Celeron
Celeron is a brand name given by Intel Corp. to a number of different x86 computer microprocessor models targeted at budget personal computers....
brand names. The Core microarchitecture is Intel's final mainstream processor line to use FSB
FSB
FSB may refer to:in business and economics:* Financial Stability Board, an international group of financial authorities* Swedbank, a retail banking group* Fuqua School of Business, a business school...
, with all later Intel processors based on Nehalem and following Intel microarchitectures exclusively using the QPI or DMI bus. Improvements from the Intel Core processors were:
- A 14-stage instruction pipeline to achieve significantly higher clock speeds than the Core processsors.
- SSSE3SSSE3Supplemental Streaming SIMD Extensions 3 is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology.- History :...
support for all models and SSE4.1 support for all Core 2 models manufactured at a 45 nm lithography. - An x86-64 (64-bit) instruction set is added, allowing all Core 2 processors to run 64-bit applications.
- Increased FSB speed, with the FSB running from 533 MHz to 1600 MHz.
- Increased L2 cache size, with the L2 cache size ranging from 1 MB to 12 MB (Core 2 Duo processors use a shared L2 cache with Core 2 Quad processors having half of the total cache allocated to each die).
- Some mobile Core 2 Duo processors support Dynamic Front Side Bus Throttling, with the FSB running at half of its full speed in Super Low Frequency Mode, therefore reducing the core speed to half of its full speed as well. This technique allows the processors to consume less power, increasing battery life.
- Some mobile Core 2 Duo processors have Dynamic Acceleration Technology, while mobile Core 2 Quad processors support Dual Dynamic Acceleration Technology. For a mobile Core 2 Duo, this feature allows the CPU to overclock one processor core while turning off the other one. As for a mobile Core 2 Quad, two cores can be overclocked. The processor does this if an application only uses a single core or two as a minimum requirement to function effectively and the clock multiplier is only increased by 1.
P6 based chips
- CeleronCeleronCeleron is a brand name given by Intel Corp. to a number of different x86 computer microprocessor models targeted at budget personal computers....
(Covington/Mendocino/Coppermine/Tualatin variants) - Pentium ProPentium ProThe Pentium Pro is a sixth-generation x86 microprocessor developed and manufactured by Intel introduced in November 1, 1995 . It introduced the P6 microarchitecture and was originally intended to replace the original Pentium in a full range of applications...
- Pentium II Overdrive (a Pentium II chip in the 387 pin Socket 8Socket 8The Socket 8 CPU socket was used exclusively with the Intel Pentium Pro and Pentium II Overdrive computer processors. Intel discontinued Socket 8 in favor of Slot 1 with the introduction of the Pentium II.-Technical specifications:...
) - Pentium IIPentium IIThe Pentium II brand refers to Intel's sixth-generation microarchitecture and x86-compatible microprocessors introduced on May 7, 1997. Containing 7.5 million transistors, the Pentium II featured an improved version of the first P6-generation core of the Pentium Pro, which contained 5.5 million...
- Pentium II XeonXeonThe Xeon is a brand of multiprocessing- or multi-socket-capable x86 microprocessors from Intel Corporation targeted at the non-consumer server, workstation and embedded system markets.-Overview:...
- Pentium IIIPentium IIIThe Pentium III brand refers to Intel's 32-bit x86 desktop and mobile microprocessors based on the sixth-generation P6 microarchitecture introduced on February 26, 1999. The brand's initial processors were very similar to the earlier Pentium II-branded microprocessors...
- Pentium III XeonXeonThe Xeon is a brand of multiprocessing- or multi-socket-capable x86 microprocessors from Intel Corporation targeted at the non-consumer server, workstation and embedded system markets.-Overview:...
Banias/Dothan variant
- Celeron M (Banias/Shelton/Dothan variants)
- Pentium MPentium MThe Pentium M brand refers to a family of mobile single-core x86 microprocessors introduced in March 2003 , and forming a part of the Intel Carmel notebook platform under the then new Centrino brand...
- A100/A110Intel A100Stealey is the codename for a low-power x86 architecture microprocessor based on a Dothan core derived from the Intel Pentium M, built on a 90 nm process with 512 KB L2 cache and 400 MT/s front side bus . It was branded as Intel A100 and Intel A110 and appeared as part of the McCaslin platform...
- EP80579
Yonah variant
- Celeron M 400 series
- Core Solo/DuoIntel CoreYonah was the code name for Intel's first generation of 65 nm process mobile microprocessors, based on the Banias/Dothan-core Pentium M microarchitecture. SIMD performance has been improved through the addition of SSE3 instructions and improvements to SSE and SSE2 implementations, while integer...
- Pentium Dual-Core T2060/T2080/T2130
- Xeon LV/ULVXeonThe Xeon is a brand of multiprocessing- or multi-socket-capable x86 microprocessors from Intel Corporation targeted at the non-consumer server, workstation and embedded system markets.-Overview:...
(Sossaman)
While all these chips are technically derivatives of the Pentium Pro the architecture has gone through several radical changes since its inception.
See also
- Core microarchitecture
- Bob ColwellBob ColwellRobert P. "Bob" Colwell is an electrical engineer who worked at Intel and is now Deputy Director of the Microsystems Technology Office at DARPA. He was the chief IA-32 architect on the Pentium Pro, Pentium II, Pentium III, and Pentium 4 microprocessors. Bob retired from Intel in 2000...
- List of Intel CPU microarchitectures