The POWER4 is a microprocessor

Microprocessor

A microprocessor incorporates the functions of a computer's central processing unit on a single integrated circuit, or at most a few integrated circuits. It is a multipurpose, programmable device that accepts digital data as input, processes it according to instructions stored in its memory, and...

 developed by International Business Machines (IBM) that implemented the 64-bit

64-bit

64-bit is a word size that defines certain classes of computer architecture, buses, memory and CPUs, and by extension the software that runs on them. 64-bit CPUs have existed in supercomputers since the 1970s and in RISC-based workstations and servers since the early 1990s...

 PowerPC

PowerPC

PowerPC is a RISC architecture created by the 1991 Apple–IBM–Motorola alliance, known as AIM...

 and PowerPC AS instruction set architectures. Released in 2001, the POWER4 succeeded the POWER3

POWER3

The POWER3 is a microprocessor, designed and exclusively manufactured by IBM, that implemented the 64-bit version of the PowerPC instruction set architecture , including all of the optional instructions of the ISA such as the POWER2. It was introduced on 5 October 1998, debuting in the RS/6000 43P...

 and RS64 microprocessors, and was used in RS/6000

RS/6000

RISC System/6000, or RS/6000 for short, is a family of RISC and UNIX based servers, workstations and supercomputers made by IBM in the 1990s. The RS/6000 family replaced the IBM RT computer platform in February 1990 and was the first computer line to see the use of IBM's POWER and PowerPC based...

 and AS/400 computers, ending a separate development of PowerPC microprocessors for the AS/400. The POWER4 was a multicore

Multicore

Multicore may refer to:* Multi-core processor ** Multicore Association, founded in 2005, a non-profit, industry consortium focused on multicore technology* multicore cable, a generic term for an electrical cable that has multiple cores...

 microprocessor, with two cores on a single die, the first non-embedded microprocessor to do so. The original POWER4 had a clock speed of 1.1 and 1.3 GHz, while an enhanced version, the POWER4+, reached a clock speed of 1.9 GHz. The PowerPC 970

PowerPC 970

The PowerPC 970, PowerPC 970FX, PowerPC 970GX, and PowerPC 970MP, are 64-bit Power Architecture processors from IBM introduced in 2002. When used in Apple Inc. machines, they were dubbed the PowerPC G5....

 is a derivative of the POWER4.

Functional layout

The POWER4 has a unified L2 cache, divided into three equal parts. Each has its own independent L2 controller which can feed 32 bytes of data per cycle. The Core Interface Unit (CIU) connects each L2 controller to either the data cache or instruction cache in either of the two processors. The Non-Cacheable (NC) Unit is responsible for handling instruction serializing functions and performing any noncacheable operations in the storage topology. There is an L3 cache controller, but the actual memory is off-chip. The GX bus controller controls I/O device communications, and there are two 4-byte wide GX buses, one incoming and the other outgoing. The Fabric Controller is the master controller for the network of buses, controlling communications for both L1/L2 controllers, communications between POWER4 chips {4-way, 8-way, 16-way, 32-way} and POWER4 MCM’s. Trace-and-Debug, used for First Failure Data Capture, is provided. There is also a Built In Self Test function (BIST) and Performance Monitoring Unit (PMU). Power-on reset

Power-on reset

A power-on reset generator is a microcontroller or microprocessor peripheral that generates a reset signal when power is applied to the device...

 (POR) is supported.

Execution units

The POWER4 implements a superscalar

Superscalar

A superscalar CPU architecture implements a form of parallelism called instruction level parallelism within a single processor. It therefore allows faster CPU throughput than would otherwise be possible at a given clock rate...

 microarchitecture

Microarchitecture

In computer engineering, microarchitecture , also called computer organization, is the way a given instruction set architecture is implemented on a processor. A given ISA may be implemented with different microarchitectures. Implementations might vary due to different goals of a given design or...

 through high-frequency speculative

Speculative execution

Speculative execution in computer systems is doing work, the result of which may not be needed. This performance optimization technique is used in pipelined processors and other systems.-Main idea:...

 out-of-order execution

Out-of-order execution

In computer engineering, out-of-order execution is a paradigm used in most high-performance microprocessors to make use of instruction cycles that would otherwise be wasted by a certain type of costly delay...

 using eight independent execution units. They are: two floating-point units (FP1-2), two load-store units (LD1-2), two fixed-point units (FX1-2), a branch unit (BR), and a conditional-register unit (CR). These execution units can complete up to eight operations per clock (not including the BR and CR units):

• each floating point unit can complete one fused multiply–add per clock (two operations),
• each load–store unit can complete one instruction per clock,
• each fixed-point unit can complete one instruction per clock.

The pipeline stages are:

• Branch Prediction
• Instruction Fetch
• Decode, Crack and Group Formation
• Group Dispatch and Instruction Issue
• Load–Store Unit Operation
  • Load Hit Store
  • Store Hit Load
  • Load Hit Load
• Instruction Execution Pipeline

Multi-chip configuration

The POWER4 also came in a configuration using a multi-chip module

Multi-Chip Module

A multi-chip module is a specialized electronic package where multiple integrated circuits , semiconductor dies or other discrete components are packaged onto a unifying substrate, facilitating their use as a single component...

(MCM) containing four POWER4 dies in a single package, with up to 128 MB of shared L3 ECC cache per MCM.

Parametrics

POWER4 180 nm@CMOS 8S3 SOI

Clock GHz	1.3 GHz
Power	115 W	1.5 V @ 1.1 GHz
Transistors		174 million
Gate L	90 nm
Gate oxide		2.3 nm
Metal-layer	pitch	thickness
M1	500 nm	310 nm
M2	630 nm	310 nm
M3-M5	630 nm	420 nm
M6(MQ)	1260 nm	920 nm
M7(LM)	1260 nm	920 nm
Dielectric	~4.2
Vdd	1.6 V

POWER4+

The POWER4+ was an improved version of the POWER4 that ran at up to 1.9 GHz. It contained 184 million transistors, measured 267 mm², and was fabricated in a 0.13 µm SOI CMOS process with eight layers of copper interconnect.