HyperSPARC
Encyclopedia
The hyperSPARC, code-named "Pinnacle", is a microprocessor
that implements the SPARC Version 8
instruction set architecture (ISA) developed by Ross Technology for Cypress Semiconductor
.
The hyperSPARC was introduced in 1993, and competed with the Sun Microsystems
SuperSPARC
. Raju Vegesna was the microarchitect. The hyperSPARC was Sun Microsystem's primary competitor in the mid-1990s. When Fujitsu acquired Ross from Cypress, the hyperSPARC was considered to be more important by its new owner than the SPARC64
developed by HAL Computer Systems
, also a Fujitsu subsidiary, a view which was shared with analysts.
microprocessor. It had four execution units: an integer unit, a floating-point unit, a load/store unit and a branch unit. The hyperSPARC has an on-die 8 KB instruction cache, from which two instructions were fetched per cycle and decoded. The decoder could not decode new instructions if the previously decoded instructions were not issued to the execution units.
The integer register file
contained 136 registers, providing eight register window
s, a feature defined in the SPARC ISA. It had two read ports. The integer unit had a four-stage pipeline
, of which two stages were added so the pipeline would be equal to all non-floating-point pipelines. Integer multiply and divide, instructions added in the V8 version of the SPARC architecture, had a 18- and 37-cycle latency, respectively, and stalled the pipeline until they were completed.
The microprocessor supported multiprocessing
on MBus systems.
, except for the last iteration, which was fabricated by NEC
.
(MCM) with a pin grid array
(PGA).
Microprocessor
A microprocessor incorporates the functions of a computer's central processing unit on a single integrated circuit, or at most a few integrated circuits. It is a multipurpose, programmable device that accepts digital data as input, processes it according to instructions stored in its memory, and...
that implements the SPARC Version 8
SPARC
SPARC is a RISC instruction set architecture developed by Sun Microsystems and introduced in mid-1987....
instruction set architecture (ISA) developed by Ross Technology for Cypress Semiconductor
Cypress Semiconductor
Cypress Semiconductor Corporation is a Silicon Valley-based semiconductor design and manufacturing company founded by T. J. Rodgers and others from Advanced Micro Devices. It was formed in 1982 with backing by Sevin Rosen and went public in 1986. The company initially focused on the design and...
.
The hyperSPARC was introduced in 1993, and competed with the Sun Microsystems
Sun Microsystems
Sun Microsystems, Inc. was a company that sold :computers, computer components, :computer software, and :information technology services. Sun was founded on February 24, 1982...
SuperSPARC
SuperSPARC
The SuperSPARC is a microprocessor that implements the SPARC V8 instruction set architecture developed by Sun Microsystems. 33 and 40 MHz versions were introduced in 1992. The SuperSPARC contained 3.1 million transistors. It was fabricated by Texas Instruments at Miho, Japan in a 0.8 micrometre...
. Raju Vegesna was the microarchitect. The hyperSPARC was Sun Microsystem's primary competitor in the mid-1990s. When Fujitsu acquired Ross from Cypress, the hyperSPARC was considered to be more important by its new owner than the SPARC64
SPARC64
SPARC64 is a microprocessor developed by HAL Computer Systems and fabricated by Fujitsu. It implements the SPARC V9 instruction set architecture , the first microprocessor to do so. SPARC64 was HAL's first microprocessor and was the first in the SPARC64 brand. It operates at 101 and 118 MHz...
developed by HAL Computer Systems
HAL Computer Systems
HAL Computer Systems, Inc was a Campbell, California-based computer manufacturer founded in 1990 by Andrew Heller, a principal designer of the original IBM POWER architecture...
, also a Fujitsu subsidiary, a view which was shared with analysts.
Description
The hyperSPARC was a two-way superscalarSuperscalar
A superscalar CPU architecture implements a form of parallelism called instruction level parallelism within a single processor. It therefore allows faster CPU throughput than would otherwise be possible at a given clock rate...
microprocessor. It had four execution units: an integer unit, a floating-point unit, a load/store unit and a branch unit. The hyperSPARC has an on-die 8 KB instruction cache, from which two instructions were fetched per cycle and decoded. The decoder could not decode new instructions if the previously decoded instructions were not issued to the execution units.
The integer register file
Register file
A register file is an array of processor registers in a central processing unit . Modern integrated circuit-based register files are usually implemented by way of fast static RAMs with multiple ports...
contained 136 registers, providing eight register window
Register window
In computer engineering, the use of register windows is a technique to improve the performance of a particularly common operation, the procedure call...
s, a feature defined in the SPARC ISA. It had two read ports. The integer unit had a four-stage pipeline
Instruction pipeline
An instruction pipeline is a technique used in the design of computers and other digital electronic devices to increase their instruction throughput ....
, of which two stages were added so the pipeline would be equal to all non-floating-point pipelines. Integer multiply and divide, instructions added in the V8 version of the SPARC architecture, had a 18- and 37-cycle latency, respectively, and stalled the pipeline until they were completed.
The microprocessor supported multiprocessing
Multiprocessing
Multiprocessing is the use of two or more central processing units within a single computer system. The term also refers to the ability of a system to support more than one processor and/or the ability to allocate tasks between them...
on MBus systems.
Physical
The hyperSPARC consisted of 1.2 million transistors. It was fabricated by Cypress in their 0.65 µm, two-layer metal, complementary metal–oxide–semiconductor (CMOS) process. Later iterations of the hyperSPARC have more transistors due to new features, and were ported to newer processes. They were fabricated by FujitsuFujitsu
is a Japanese multinational information technology equipment and services company headquartered in Tokyo, Japan. It is the world's third-largest IT services provider measured by revenues....
, except for the last iteration, which was fabricated by NEC
NEC
, a Japanese multinational IT company, has its headquarters in Minato, Tokyo, Japan. NEC, part of the Sumitomo Group, provides information technology and network solutions to business enterprises, communications services providers and government....
.
Packaging
The hyperSPARC was a multi-chip design. It was packaged in a ceramic multi-chip moduleMulti-Chip Module
A multi-chip module is a specialized electronic package where multiple integrated circuits , semiconductor dies or other discrete components are packaged onto a unifying substrate, facilitating their use as a single component...
(MCM) with a pin grid array
Pin grid array
A pin grid array, often abbreviated PGA, is a type of integrated circuit packaging. In a PGA, the package is square or roughly square, and the pins are arranged in a regular array on the underside of the package...
(PGA).
Chipsets
The hyperSPARC used the Cypress SparcSet chipset which was introduced in late July 1992. It was developed by Santa Clara, California start-up Nimbus Technologies, Inc. for Cypress, who fabricated the design. SparcSet was also compatible with other SPARC microprocessors.Further reading
- "Ross Previews Pinnacle SPARC Design". (25 March 1992). Microprocessor Report, vol. 6, no. 4.
- "TI and Cypress/Ross Battle for SPARC Leadership". (27 May 1992). Microprocessor Report, vol. 6, no. 7.
- "Ross Finally Ships HyperSPARC". (15 November 1993). Microprocessor Report, vol. 7, no. 15.
- "Enhanced HyperSparc Challenges UltraSparc". (4 December 1995). Microprocessor Report, vol. 9, no. 16.