PowerPC A2
Encyclopedia
The PowerPC A2 is a massively multicore capable and multithreaded 64-bit
Power Architecture
processor core designed by IBM
using the Power ISA v.2.06 specification. Versions of processors based on the A2 core range from a 2.3 GHz
version with 16 cores consuming 65 W
to a less powerful, four core version, consuming 20 W at 1.4 GHz. Each A2 core is capable of four-way multithreading and have 16+16 instruction and data cache per core.
processor", is designed as hybrid between regular networking processors
, doing switching
and routing
and a typical server processor, that is manipulating and packaging data. It was revealed February 8 2010, at ISSCC 2010
.
Each chip has 8 MB of cache
as well a multitude of task-specific engines besides the general-purpose processors, such as XML
, cryptography
, compression
and regular expression
accelerators each with MMUs of their own, four 10 Gigabit Ethernet
ports and two PCIe lanes
. Up to four chips can be linked in a SMP
system without any additional support chips. The chips are said to be extremely complex, and use 1.43 billion transistors on a die
size of 428 mm² fabricated using a 45 nm process. The processors are in a late development stage and finalized products will be available at a later, unknown date. IBM says it will market the processors to customers.
processor is a 18 core chip running at 1.6 GHz with special features for fast thread context switching, quad pumped floating point unit, 5D torus network and 10 Gbit I/O. The cores are linked by a crossbar switch
at half core speed to a 32 MB eDRAM
L2 cache
. A Blue Gene/Q chip have two DDR3
memory controllers running at 1.33 GHz, supporting up to 16 GB RAM.
It uses 16 cores for computing, and one core for running an operating system. This core will take care of interrupt
s, asynchronous I/O
, MPI pacing
and RAS
functionality and will be remapped to a functional core in case of failure of one of the other cores. The 18th core is used as a spare in case one of the other cores are permanently damaged, like in manufacturing, but could be used as hot spare
as well. The Blue Gene/Q chip is manufactured on IBM's copper SOI process at 45 nm, and will deliver 205 GFLOPS
at 1.6 GHz and draw 55 watts. It is 19×19 mm large (359.5 mm²) and comprise 1.47 billion transistors.
64-bit
64-bit is a word size that defines certain classes of computer architecture, buses, memory and CPUs, and by extension the software that runs on them. 64-bit CPUs have existed in supercomputers since the 1970s and in RISC-based workstations and servers since the early 1990s...
Power Architecture
Power Architecture
Power Architecture is a broad term to describe similar RISC instruction sets for microprocessors developed and manufactured by such companies as IBM, Freescale, AMCC, Tundra and P.A. Semi...
processor core designed by IBM
IBM
International Business Machines Corporation or IBM is an American multinational technology and consulting corporation headquartered in Armonk, New York, United States. IBM manufactures and sells computer hardware and software, and it offers infrastructure, hosting and consulting services in areas...
using the Power ISA v.2.06 specification. Versions of processors based on the A2 core range from a 2.3 GHz
Hertz
The hertz is the SI unit of frequency defined as the number of cycles per second of a periodic phenomenon. One of its most common uses is the description of the sine wave, particularly those used in radio and audio applications....
version with 16 cores consuming 65 W
Watt
The watt is a derived unit of power in the International System of Units , named after the Scottish engineer James Watt . The unit, defined as one joule per second, measures the rate of energy conversion.-Definition:...
to a less powerful, four core version, consuming 20 W at 1.4 GHz. Each A2 core is capable of four-way multithreading and have 16+16 instruction and data cache per core.
PowerEN
The PowerEN (Power Edge of Network), or the "wire-speedWire speed
Wire speed or wirespeed is a non-formal language term referring to the hypothetical peak physical layer net bitrate of a cable combined with a certain digital communication device/interface/port...
processor", is designed as hybrid between regular networking processors
Network processor
A network processor is an integrated circuit which has a feature set specifically targeted at the networking application domain.Network processors are typically software programmable devices and would have generic characteristics similar to general purpose central processing units that are commonly...
, doing switching
Packet switching
Packet switching is a digital networking communications method that groups all transmitted data – regardless of content, type, or structure – into suitably sized blocks, called packets. Packet switching features delivery of variable-bit-rate data streams over a shared network...
and routing
Routing
Routing is the process of selecting paths in a network along which to send network traffic. Routing is performed for many kinds of networks, including the telephone network , electronic data networks , and transportation networks...
and a typical server processor, that is manipulating and packaging data. It was revealed February 8 2010, at ISSCC 2010
International Solid-State Circuits Conference
International Solid-State Circuits Conference is a global forum for presentation of advances in solid-state circuits and Systems-on-a-Chip. The Conference offers a unique opportunity for engineers working at the cutting edge of IC design to maintain technical currency, and to network with leading...
.
Each chip has 8 MB of cache
CPU cache
A CPU cache is a cache used by the central processing unit of a computer to reduce the average time to access memory. The cache is a smaller, faster memory which stores copies of the data from the most frequently used main memory locations...
as well a multitude of task-specific engines besides the general-purpose processors, such as XML
XML
Extensible Markup Language is a set of rules for encoding documents in machine-readable form. It is defined in the XML 1.0 Specification produced by the W3C, and several other related specifications, all gratis open standards....
, cryptography
Cryptography
Cryptography is the practice and study of techniques for secure communication in the presence of third parties...
, compression
Data compression
In computer science and information theory, data compression, source coding or bit-rate reduction is the process of encoding information using fewer bits than the original representation would use....
and regular expression
Regular expression
In computing, a regular expression provides a concise and flexible means for "matching" strings of text, such as particular characters, words, or patterns of characters. Abbreviations for "regular expression" include "regex" and "regexp"...
accelerators each with MMUs of their own, four 10 Gigabit Ethernet
10 Gigabit Ethernet
The 10 gigabit Ethernet computer networking standard was first published in 2002. It defines a version of Ethernet with a nominal data rate of 10 Gbit/s , ten times faster than gigabit Ethernet.10 gigabit Ethernet defines only full duplex point to point links which are generally connected by...
ports and two PCIe lanes
PCI Express
PCI Express , officially abbreviated as PCIe, is a computer expansion card standard designed to replace the older PCI, PCI-X, and AGP bus standards...
. Up to four chips can be linked in a SMP
Symmetric multiprocessing
In computing, symmetric multiprocessing involves a multiprocessor computer hardware architecture where two or more identical processors are connected to a single shared main memory and are controlled by a single OS instance. Most common multiprocessor systems today use an SMP architecture...
system without any additional support chips. The chips are said to be extremely complex, and use 1.43 billion transistors on a die
Die (integrated circuit)
A die in the context of integrated circuits is a small block of semiconducting material, on which a given functional circuit is fabricated.Typically, integrated circuits are produced in large batches on a single wafer of electronic-grade silicon or other semiconductor through processes such as...
size of 428 mm² fabricated using a 45 nm process. The processors are in a late development stage and finalized products will be available at a later, unknown date. IBM says it will market the processors to customers.
Blue Gene/Q
The Blue Gene/QBlue Gene
Blue Gene is a computer architecture project to produce several supercomputers, designed to reach operating speeds in the PFLOPS range, and currently reaching sustained speeds of nearly 500 TFLOPS . It is a cooperative project among IBM Blue Gene is a computer architecture project to produce...
processor is a 18 core chip running at 1.6 GHz with special features for fast thread context switching, quad pumped floating point unit, 5D torus network and 10 Gbit I/O. The cores are linked by a crossbar switch
Crossbar switch
In electronics, a crossbar switch is a switch connecting multiple inputs to multiple outputs in a matrix manner....
at half core speed to a 32 MB eDRAM
EDRAM
eDRAM stands for "embedded DRAM", a capacitor-based dynamic random access memory integrated on the same die as an ASIC or processor. The cost-per-bit is higher than for stand-alone DRAM chips but in many applications the performance advantages of placing the eDRAM on the same chip as the processor...
L2 cache
CPU cache
A CPU cache is a cache used by the central processing unit of a computer to reduce the average time to access memory. The cache is a smaller, faster memory which stores copies of the data from the most frequently used main memory locations...
. A Blue Gene/Q chip have two DDR3
DDR3 SDRAM
In computing, DDR3 SDRAM, an abbreviation for double data rate type three synchronous dynamic random access memory, is a modern kind of dynamic random access memory with a high bandwidth interface. It is one of several variants of DRAM and associated interface techniques used since the early 1970s...
memory controllers running at 1.33 GHz, supporting up to 16 GB RAM.
It uses 16 cores for computing, and one core for running an operating system. This core will take care of interrupt
Interrupt
In computing, an interrupt is an asynchronous signal indicating the need for attention or a synchronous event in software indicating the need for a change in execution....
s, asynchronous I/O
Input/output
In computing, input/output, or I/O, refers to the communication between an information processing system , and the outside world, possibly a human, or another information processing system. Inputs are the signals or data received by the system, and outputs are the signals or data sent from it...
, MPI pacing
Message Passing Interface
Message Passing Interface is a standardized and portable message-passing system designed by a group of researchers from academia and industry to function on a wide variety of parallel computers...
and RAS
Reliability, Availability and Serviceability
reliability, availability, and serviceability are computer hardware engineering terms. It originated from IBM to advertise the robustness of their mainframe computers. The concept is often known by the acronym RAS....
functionality and will be remapped to a functional core in case of failure of one of the other cores. The 18th core is used as a spare in case one of the other cores are permanently damaged, like in manufacturing, but could be used as hot spare
Hot spare
A hot spare or hot standby is used as a failover mechanism to provide reliability in system configurations. The hot spare is active and connected as part of a working system. When a key component fails, the hot spare is switched into operation...
as well. The Blue Gene/Q chip is manufactured on IBM's copper SOI process at 45 nm, and will deliver 205 GFLOPS
FLOPS
In computing, FLOPS is a measure of a computer's performance, especially in fields of scientific calculations that make heavy use of floating-point calculations, similar to the older, simpler, instructions per second...
at 1.6 GHz and draw 55 watts. It is 19×19 mm large (359.5 mm²) and comprise 1.47 billion transistors.