POWER3
Encyclopedia
Microprocessor
A microprocessor incorporates the functions of a computer's central processing unit on a single integrated circuit, or at most a few integrated circuits. It is a multipurpose, programmable device that accepts digital data as input, processes it according to instructions stored in its memory, and...
, designed and exclusively manufactured by IBM
IBM
International Business Machines Corporation or IBM is an American multinational technology and consulting corporation headquartered in Armonk, New York, United States. IBM manufactures and sells computer hardware and software, and it offers infrastructure, hosting and consulting services in areas...
, that implemented the 64-bit version of the PowerPC
PowerPC
PowerPC is a RISC architecture created by the 1991 Apple–IBM–Motorola alliance, known as AIM...
instruction set architecture (ISA), including all of the optional instructions of the ISA (at the time) such as the POWER2
POWER2
The POWER2, originally named RIOS2, is a processor designed by IBM that implemented the POWER instruction set architecture. The POWER2 was the successor of the POWER1, debuting in September 1993 within IBM's RS/6000 systems. When introduced, the POWER2 was the fastest microprocessor, surpassing the...
. It was introduced on 5 October 1998, debuting in the RS/6000 43P Model 260
RS/6000
RISC System/6000, or RS/6000 for short, is a family of RISC and UNIX based servers, workstations and supercomputers made by IBM in the 1990s. The RS/6000 family replaced the IBM RT computer platform in February 1990 and was the first computer line to see the use of IBM's POWER and PowerPC based...
, a high-end graphics workstation. The POWER3 was originally supposed to be called the PowerPC 630 but was renamed, probably to differentiate the server-oriented POWER
IBM POWER
POWER is a reduced instruction set computer instruction set architecture developed by IBM. The name is an acronym for Performance Optimization With Enhanced RISC....
processors it replaced from the more consumer-oriented 32-bit PowerPCs. The POWER3 was the successor of the P2SC derivative of the POWER2 and completed IBM's long-delayed transition from POWER to PowerPC, which was originally scheduled to conclude in 1995. The POWER3 was used in IBM RS/6000
RS/6000
RISC System/6000, or RS/6000 for short, is a family of RISC and UNIX based servers, workstations and supercomputers made by IBM in the 1990s. The RS/6000 family replaced the IBM RT computer platform in February 1990 and was the first computer line to see the use of IBM's POWER and PowerPC based...
servers and workstations at 200 MHz. It competed with the Digital Equipment Corporation
Digital Equipment Corporation
Digital Equipment Corporation was a major American company in the computer industry and a leading vendor of computer systems, software and peripherals from the 1960s to the 1990s...
(DEC) Alpha 21264
Alpha 21264
The Alpha 21264 was a Digital Equipment Corporation RISC microprocessor introduced in October, 1996. The 21264 implemented the Alpha instruction set architecture .- Description :...
and the Hewlett-Packard
Hewlett-Packard
Hewlett-Packard Company or HP is an American multinational information technology corporation headquartered in Palo Alto, California, USA that provides products, technologies, softwares, solutions and services to consumers, small- and medium-sized businesses and large enterprises, including...
(HP) PA-8500.
Description
The POWER3 was based on the PowerPC 620, an earlier 64-bit PowerPC implementation that was late, under-performing and commercially unsuccessful. Like the PowerPC 620, the POWER3 has three fixed-point unitsArithmetic logic unit
In computing, an arithmetic logic unit is a digital circuit that performs arithmetic and logical operations.The ALU is a fundamental building block of the central processing unit of a computer, and even the simplest microprocessors contain one for purposes such as maintaining timers...
, but the single floating-point unit (FPU) was replaced with two floating-point fused multiply–add units, and an extra load-store unit was added (for a total of two) to improve floating-point performance. The POWER3 is a superscalar
Superscalar
A superscalar CPU architecture implements a form of parallelism called instruction level parallelism within a single processor. It therefore allows faster CPU throughput than would otherwise be possible at a given clock rate...
design that executed instructions out of order
Out-of-order execution
In computer engineering, out-of-order execution is a paradigm used in most high-performance microprocessors to make use of instruction cycles that would otherwise be wasted by a certain type of costly delay...
. It has a seven-stage integer pipeline, a minimal eight-stage load/store pipeline and a ten-stage floating-point pipeline.
The front end consists of two stages: fetch and decode. During the first stage, eight instructions were fetched from a 32 KB instruction cache and placed in a 12-entry instruction buffer. During the second stage, four instructions were taken from the instruction buffer, decoded, and issued to instruction queues. Restrictions on instruction issue are few: of the two integer integer instruction queues, only one can accept one instruction, the other can accept up to four, as does the floating-point instruction queue. If the queues do not have enough unused entries, instructions cannot be issued. The front end has a short pipeline, resulting in a small three-cycle branch misprediction penalty.
In stage three, instructions in the instruction queues that are ready for execution have their operands read from the register files. The general-purpose register file contains 48 registers, of which 32 are general-purpose registers and 16 are rename registers for register renaming
Register renaming
In computer architecture, register renaming refers to a technique used to avoid unnecessary serialization of program operations imposed by the reuse of registers by those operations.-Problem definition:...
. To reduce the number of ports required to provide data and receive results, the general purpose register file is duplicated so that there are two copies, the first supporting three integer execution units and the second supporting the two load/store units. This scheme was similar to a contemporary microprocessor, the DEC
Digital Equipment Corporation
Digital Equipment Corporation was a major American company in the computer industry and a leading vendor of computer systems, software and peripherals from the 1960s to the 1990s...
Alpha 21264
Alpha 21264
The Alpha 21264 was a Digital Equipment Corporation RISC microprocessor introduced in October, 1996. The 21264 implemented the Alpha instruction set architecture .- Description :...
, but was simpler as it did not require an extra clock cycle to synchronize the two copies due to the POWER3's higher cycle times. The floating-point register file contains 56 registers, of which 32 are floating-point registers and 24 rename registers. Compared to the PowerPC 620, there were more rename registers, which allowed more instructions to be executed out of order, improving performance.
Execution begins in stage four. The instruction queues dispatch up to eight instructions to the execution units. Integer instructions are executed in three integer execution units (termed "fixed-point units" by IBM). Two of the units are identical and execute all integer instructions except for multiply and divide. All instructions executed by them have a one-cycle latency. The third unit executes multiply and divide instructions. These instructions are not pipelined and have multi-cycle latencies. 64-bit multiply has a nine-cycle latency and 64-bit divide has a 37-cycle latency.
Floating-point instructions are executed in two floating-point units (FPUs). The FPUs are capable of fused multiply–add, where multiplication and addition is performed simultaneously. Such instructions, along with individual add and multiply, have a four-cycle latency. Divide and square-root instructions are executed in the same FPUs, but are assisted by specialized hardware. Single-precision (32-bit) divide and square-root instructions have a 14-cycle latency, whereas double-precision (64-bit) divide and square-root instructions have an 18-cycle and a 22-cycle latency, respectively.
After execution is completed, the instructions are held in buffers before being committed and made visible to software. Execution finishes in stage five for integer instructions and stage eight and for floating-point. Committing occurs during stage six for integers, stage nine for floating-point. Writeback occurs in the stage after commit. The POWER3 can retire up to four instructions per cycle.
The PowerPC 620 data cache was optimized for technical and scientific applications. Its capacity was doubled to 64 KB, to improve the cache-hit rate; the cache was dual-ported, implemented by interleaving eight banks, to enable two loads or two stores to be performed in one cycle in certain cases; and the line-size was increased to 128-bytes. The L2 cache bus was doubled in width to 256 bits to compensate for the larger cache line size and to retain a four-cycle latency for cache refills.
The POWER3 contained 15 million transistors on a 270 mm2 die. It was fabricated in IBM's CMOS-6S2 process, a complementary metal–oxide–semiconductor process that is a hybrid of 0.25 µm feature sizes and 0.35 µm metal layers. The process features five layers of aluminium. It was packaged in the same 1,088-column ceramic column grid array as the P2SC, but with a different pin out.
POWER3-II
POWER4
The POWER4 is a microprocessor developed by International Business Machines that implemented the 64-bit PowerPC and PowerPC AS instruction set architectures. Released in 2001, the POWER4 succeeded the POWER3 and RS64 microprocessors, and was used in RS/6000 and AS/400 computers, ending a separate...
in 2001.