DDR4 SDRAM
Encyclopedia
In computing
, DDR4 SDRAM, an abbreviation for double data rate
type four synchronous dynamic random-access memory, is a type of dynamic random-access memory (DRAM) with a high bandwidth
interface currently under development and expected market release in 2012. As a "next generation" successor to DDR3 SDRAM
, it is one of several variants of DRAM used since the early 1970s. It is not directly compatible with any earlier type of random access memory (RAM) due to different signaling voltages, timings, physical interface and other factors.
DDR4 itself is a DRAM interface specification. Its primary benefits compared to DDR3 include a higher range of clock frequencies and data transfer rates (2133–4266 MT/s compared to DDR3's 800–2133) and significantly lower voltage
(1.2 - 1.05 V for DDR4, compared to 1.5 – 1.2 V for DDR3). DDR4 also anticipates a change in topology
– it discards dual and triple channel
approaches in favor of point-to-point where each channel in the memory controller
is connected to a single module. Switched memory banks are also an anticipated option for servers.
began working on a successor to DDR3 around 2005, about 2 years before the launch of DDR3 in 2007. The high-level architecture of DDR4 was planned for completion in 2008 and, as of 2007, was said by JEDEC's Future DRAM task group chairman to be "on time".
The final specification is expected in the second half of 2011, shortly before DDR4's commercial launch. Some advance information was published in 2007, and a guest speaker from Qimonda
provided further public details in a presentation at the August 2008 San Francisco Intel Developer Forum
(IDF). DDR4 was described as involving a 30 nm process at 1.2 volts, with bus frequencies of 2133 MT/s "regular" speed and 3200 MT/s "enthusiast" speed, and reaching market in 2012, before transitioning to 1 volt in 2013.
Subsequently, further details were revealed at MemCon 2010, Tokyo
(a computer memory industry event), at which a presentation by a JEDEC director titled "Time to rethink DDR4" with a slide titled "New roadmap: More realistic roadmap is 2015" led some websites to report that the introduction of DDR4 was probably or definitely delayed until 2015. However, DDR4 test samples were announced in line with the original schedule in early 2011 at which time manufacturers began to advise that large scale commercial production and release to market was scheduled for 2012.
DDR4 is expected to represent 5% of the DRAM market in 2013, and to reach mass market adoption and 50% market penetration
around 2015; the latter is comparable with the approximately 5 years taken for DDR3 to achieve mass market transition over DDR2. In part, this is because changes required to other components would impact all other parts of computer systems, which would need to be updated to work with DDR4.
In February 2009, Samsung
validated 40 nm DRAM chips, considered a "significant step" towards DDR4 development since in 2009, DRAM chips were only beginning to migrate to a 50 nm process. In January 2011, Samsung
announced the completion and release for testing of a 2 GB DDR4 DRAM module based on a process between 30 and 39 nm. It has a maximum data transfer rate of 2133 Mb/s at 1.2 V, uses pseudo open drain technology (adapted from graphics DDR
memory) and draws 40% less power than an equivalent DDR3 module.
Three months later in April 2011, Hynix
announced the production of 2 GB
DDR4 modules at 2400 MT/s, also running at 1.2 V on a process between 30 and 39 nm (exact process unspecified), adding that it anticipated commencing high volume production in the second half of 2012. Semiconductor processes for DDR4 are expected to transition to sub-30 nm at some point between late 2012 and 2014.
or less, versus the 1.5 V of DDR3 chips, and have in excess of 2 billion data transfers per second. They are expected to be introduced at clock speeds of 2133 MT/s, estimated to rise to a potential 4266 MT/s and lowered voltage of 1.05 V by 2013. DDR4 is likely to be initially commercialized using 32 – 36 nm processes
, and according to a roadmap by PC Watch (Japan) and comments by Samsung
, as 4 Gbit chips. Increased memory density was also anticipated, possibly using TSV ("through-silicon via
") or other 3D stacking processes
. The DDR4 specification will include standardized 3D stacking "from the start" according to JEDEC. X-bit Labs commented that "as a result DDR4 memory chips with very high density will become relatively inexpensive". Prefetch
an 8n prefetch with bank groups, including the use of two or four selectable bank groups.
DDR4 also anticipates a change in topology
. It discards dual and triple channel
approaches (used since the original first generation DDR
) in favor of point-to-point
where each channel in the memory controller
is connected to a single module. This mirrors the trend also seen in the earlier transition from PCI to PCI Express
, where parallelism was moved from the interface to the controller, and is likely to simplify timing in modern high-speed data buses. Switched memory banks are also an anticipated option for servers.
The minimum clock speed of 2133 MT/s was said to be due to progress made in DDR3 speeds which, being likely to reach 2133 Mb/s, left little commercial benefit to specifying DDR4 below this speed. Techgage interpreted Samsung's January 2011 engineering sample as having CAS latency
of 13 clock cycles, described as being comparable to the move from DDR2 to DDR3.
In 2008, concerns were raised in the book Wafer Level 3-D ICs Process Technology that non-scaling analog elements such as charge pump
s and voltage regulators
, and additional circuitry "have allowed significant increases in bandwidth
but they consume much more die area". Examples include CRC
error-detection, on-die termination
, burst hardware, programmable pipelines, low impedence, and increasing need for sense amps
(attributed to a decline in bits per bitline due to low voltage). The authors noted that as a result, the amount of die used for the memory array itself has declined over time from 70-80% with SDRAM and DDR1, to 38% for DDR3 and potentially to less than 30% for DDR4.
Computing
Computing is usually defined as the activity of using and improving computer hardware and software. It is the computer-specific part of information technology...
, DDR4 SDRAM, an abbreviation for double data rate
Double data rate
In computing, a computer bus operating with double data rate transfers data on both the rising and falling edges of the clock signal. This is also known as double pumped, dual-pumped, and double transition....
type four synchronous dynamic random-access memory, is a type of dynamic random-access memory (DRAM) with a high bandwidth
Bandwidth (computing)
In computer networking and computer science, bandwidth, network bandwidth, data bandwidth, or digital bandwidth is a measure of available or consumed data communication resources expressed in bits/second or multiples of it .Note that in textbooks on wireless communications, modem data transmission,...
interface currently under development and expected market release in 2012. As a "next generation" successor to DDR3 SDRAM
DDR3 SDRAM
In computing, DDR3 SDRAM, an abbreviation for double data rate type three synchronous dynamic random access memory, is a modern kind of dynamic random access memory with a high bandwidth interface. It is one of several variants of DRAM and associated interface techniques used since the early 1970s...
, it is one of several variants of DRAM used since the early 1970s. It is not directly compatible with any earlier type of random access memory (RAM) due to different signaling voltages, timings, physical interface and other factors.
DDR4 itself is a DRAM interface specification. Its primary benefits compared to DDR3 include a higher range of clock frequencies and data transfer rates (2133–4266 MT/s compared to DDR3's 800–2133) and significantly lower voltage
Voltage
Voltage, otherwise known as electrical potential difference or electric tension is the difference in electric potential between two points — or the difference in electric potential energy per unit charge between two points...
(1.2 - 1.05 V for DDR4, compared to 1.5 – 1.2 V for DDR3). DDR4 also anticipates a change in topology
Topology (electronics)
The topology of an electronic circuit is the form taken by the network of interconnections of the circuit components. Different specific values or ratings of the components are regarded as being the same topology....
– it discards dual and triple channel
Dual-channel architecture
Multi-channel architecture is a technology that increases the transfer speed of data between the RAM and the memory controller by adding more channels of communication between them. Theoretically this multiplies the data rate by exactly the number of channels present. Dual-channel memory employs...
approaches in favor of point-to-point where each channel in the memory controller
Memory controller
The memory controller is a digital circuit which manages the flow of data going to and from the main memory. It can be a separate chip or integrated into another chip, such as on the die of a microprocessor...
is connected to a single module. Switched memory banks are also an anticipated option for servers.
Development and market history
Standards body JEDECJEDEC
The JEDEC Solid State Technology Association, formerly known as the Joint Electron Devices Engineering Council , is an independent semiconductor engineering trade organization and standardization body...
began working on a successor to DDR3 around 2005, about 2 years before the launch of DDR3 in 2007. The high-level architecture of DDR4 was planned for completion in 2008 and, as of 2007, was said by JEDEC's Future DRAM task group chairman to be "on time".
The final specification is expected in the second half of 2011, shortly before DDR4's commercial launch. Some advance information was published in 2007, and a guest speaker from Qimonda
Qimonda
Qimonda AG, was a memory company split out of Infineon Technologies on 1 May 2006, to form at the time the second largest DRAM company worldwide, according to the industry research firm Gartner Dataquest...
provided further public details in a presentation at the August 2008 San Francisco Intel Developer Forum
Intel Developer Forum
Intel Developer Forum , is a gathering of technologists to discuss Intel products and products based around Intel products. The first IDF was in 1997...
(IDF). DDR4 was described as involving a 30 nm process at 1.2 volts, with bus frequencies of 2133 MT/s "regular" speed and 3200 MT/s "enthusiast" speed, and reaching market in 2012, before transitioning to 1 volt in 2013.
Subsequently, further details were revealed at MemCon 2010, Tokyo
Tokyo
, ; officially , is one of the 47 prefectures of Japan. Tokyo is the capital of Japan, the center of the Greater Tokyo Area, and the largest metropolitan area of Japan. It is the seat of the Japanese government and the Imperial Palace, and the home of the Japanese Imperial Family...
(a computer memory industry event), at which a presentation by a JEDEC director titled "Time to rethink DDR4" with a slide titled "New roadmap: More realistic roadmap is 2015" led some websites to report that the introduction of DDR4 was probably or definitely delayed until 2015. However, DDR4 test samples were announced in line with the original schedule in early 2011 at which time manufacturers began to advise that large scale commercial production and release to market was scheduled for 2012.
DDR4 is expected to represent 5% of the DRAM market in 2013, and to reach mass market adoption and 50% market penetration
Market penetration
Market penetration is8th growth strategies of the Product-Market Growth Matrix defined by Ansoff. Market penetration occurs when a company enters/penetrates a market with current products. The best way to achieve this is by gaining competitors' customers...
around 2015; the latter is comparable with the approximately 5 years taken for DDR3 to achieve mass market transition over DDR2. In part, this is because changes required to other components would impact all other parts of computer systems, which would need to be updated to work with DDR4.
In February 2009, Samsung
Samsung
The Samsung Group is a South Korean multinational conglomerate corporation headquartered in Samsung Town, Seoul, South Korea...
validated 40 nm DRAM chips, considered a "significant step" towards DDR4 development since in 2009, DRAM chips were only beginning to migrate to a 50 nm process. In January 2011, Samsung
Samsung
The Samsung Group is a South Korean multinational conglomerate corporation headquartered in Samsung Town, Seoul, South Korea...
announced the completion and release for testing of a 2 GB DDR4 DRAM module based on a process between 30 and 39 nm. It has a maximum data transfer rate of 2133 Mb/s at 1.2 V, uses pseudo open drain technology (adapted from graphics DDR
GDDR
GDDR or Graphic Double Data Rate memory refers to memory specifically designed for use on graphics cards. GDDR is distinct from the more widely known DDR SDRAM types such as DDR3, although they share some technologies - including double data rate design - in common...
memory) and draws 40% less power than an equivalent DDR3 module.
Three months later in April 2011, Hynix
Hynix
Hynix Semiconductor Inc. chips and flash memory chips. Founded in 1983, Hynix is the world's second-largest memory chipmaker, the largest being Samsung Electronics. Formerly known as Hyundai Electronics, the company has manufacturing sites in Korea, the U.S., China and Taiwan...
announced the production of 2 GB
Gigabyte
The gigabyte is a multiple of the unit byte for digital information storage. The prefix giga means 109 in the International System of Units , therefore 1 gigabyte is...
DDR4 modules at 2400 MT/s, also running at 1.2 V on a process between 30 and 39 nm (exact process unspecified), adding that it anticipated commencing high volume production in the second half of 2012. Semiconductor processes for DDR4 are expected to transition to sub-30 nm at some point between late 2012 and 2014.
Technical description
The new chips are expected to run at 1.2 VVolt
The volt is the SI derived unit for electric potential, electric potential difference, and electromotive force. The volt is named in honor of the Italian physicist Alessandro Volta , who invented the voltaic pile, possibly the first chemical battery.- Definition :A single volt is defined as the...
or less, versus the 1.5 V of DDR3 chips, and have in excess of 2 billion data transfers per second. They are expected to be introduced at clock speeds of 2133 MT/s, estimated to rise to a potential 4266 MT/s and lowered voltage of 1.05 V by 2013. DDR4 is likely to be initially commercialized using 32 – 36 nm processes
32 nanometer
The 32 nm process is the step following the 45 nanometer process in CMOS semiconductor device fabrication. 32 nanometer refers to the average half-pitch of a memory cell at this technology level...
, and according to a roadmap by PC Watch (Japan) and comments by Samsung
Samsung
The Samsung Group is a South Korean multinational conglomerate corporation headquartered in Samsung Town, Seoul, South Korea...
, as 4 Gbit chips. Increased memory density was also anticipated, possibly using TSV ("through-silicon via
Through-silicon via
In electronic engineering, a through-silicon via is a vertical electrical connection passing completely through a silicon wafer or die...
") or other 3D stacking processes
Three-dimensional integrated circuit
In electronics, a three-dimensional integrated circuit is a chip in which two or more layers of active electronic components are integrated both vertically and horizontally into a single circuit...
. The DDR4 specification will include standardized 3D stacking "from the start" according to JEDEC. X-bit Labs commented that "as a result DDR4 memory chips with very high density will become relatively inexpensive". Prefetch
Prefetch buffer
A prefetch buffer is a data buffer employed on modern DRAM chips that allows quick and easy access to multiple data words located on a common physical row in the memory....
an 8n prefetch with bank groups, including the use of two or four selectable bank groups.
DDR4 also anticipates a change in topology
Topology (electronics)
The topology of an electronic circuit is the form taken by the network of interconnections of the circuit components. Different specific values or ratings of the components are regarded as being the same topology....
. It discards dual and triple channel
Dual-channel architecture
Multi-channel architecture is a technology that increases the transfer speed of data between the RAM and the memory controller by adding more channels of communication between them. Theoretically this multiplies the data rate by exactly the number of channels present. Dual-channel memory employs...
approaches (used since the original first generation DDR
DDR SDRAM
Double data rate synchronous dynamic random access memory is a class of memory integrated circuits used in computers. DDR SDRAM has been superseded by DDR2 SDRAM and DDR3 SDRAM, neither of which are either forward or backward compatible with DDR SDRAM, meaning that DDR2 or DDR3 memory modules...
) in favor of point-to-point
Point-to-point
Point-to-point or point to point may refer to:Computing* Point-to-point construction, an electronics assembly technique* Point-to-point * Point-to-Point Protocol , part of the Internet protocol suite...
where each channel in the memory controller
Memory controller
The memory controller is a digital circuit which manages the flow of data going to and from the main memory. It can be a separate chip or integrated into another chip, such as on the die of a microprocessor...
is connected to a single module. This mirrors the trend also seen in the earlier transition from PCI to PCI Express
PCI Express
PCI Express , officially abbreviated as PCIe, is a computer expansion card standard designed to replace the older PCI, PCI-X, and AGP bus standards...
, where parallelism was moved from the interface to the controller, and is likely to simplify timing in modern high-speed data buses. Switched memory banks are also an anticipated option for servers.
The minimum clock speed of 2133 MT/s was said to be due to progress made in DDR3 speeds which, being likely to reach 2133 Mb/s, left little commercial benefit to specifying DDR4 below this speed. Techgage interpreted Samsung's January 2011 engineering sample as having CAS latency
CAS Latency
Column Address Strobe latency, or CL, is the delay time between the moment a memory controller tells the memory module to access a particular memory column on a RAM memory module, and the moment the data from given array location is available on the module's output pins...
of 13 clock cycles, described as being comparable to the move from DDR2 to DDR3.
In 2008, concerns were raised in the book Wafer Level 3-D ICs Process Technology that non-scaling analog elements such as charge pump
Charge pump
A charge pump is a kind of DC to DC converter that uses capacitors as energy storage elements to create either a higher or lower voltage power source. Charge pump circuits are capable of high efficiencies, sometimes as high as 90–95% while being electrically simple circuits.Charge pumps use some...
s and voltage regulators
Bandgap voltage reference
A bandgap voltage reference is a temperature independent voltage reference circuit widely used in integrated circuits, usually with an output voltage around 1.25 V, close to the theoretical 1.22 eV bandgap of silicon at 0 K. This circuit concept was first published by David Hilbiber in 1964...
, and additional circuitry "have allowed significant increases in bandwidth
Bandwidth
Bandwidth is the difference between the upper and lower frequencies in a contiguous set of frequencies. It is typically measured in hertz, and may sometimes refer to passband bandwidth, sometimes to baseband bandwidth, depending on context...
but they consume much more die area". Examples include CRC
Cyclic redundancy check
A cyclic redundancy check is an error-detecting code commonly used in digital networks and storage devices to detect accidental changes to raw data...
error-detection, on-die termination
On-die termination
On-die termination is the technology where the termination resistor for impedance matching in transmission lines is located inside a semiconductor chip instead of on a printed circuit board.- Overview of electronic signal termination :...
, burst hardware, programmable pipelines, low impedence, and increasing need for sense amps
Current sense amplifier
Current sense amplifiers are special purpose amplifiers that output a voltage proportional to the current flowing in a power rail. They utilize a "current-sense resistor" to convert the load current in the power rail to a small voltage, which is then amplified by the current-sense amplifiers...
(attributed to a decline in bits per bitline due to low voltage). The authors noted that as a result, the amount of die used for the memory array itself has declined over time from 70-80% with SDRAM and DDR1, to 38% for DDR3 and potentially to less than 30% for DDR4.
See also
- Synchronous dynamic random access memorySynchronous dynamic random access memorySynchronous dynamic random access memory is dynamic random access memory that is synchronized with the system bus. Classic DRAM has an asynchronous interface, which means that it responds as quickly as possible to changes in control inputs...
– main article for DDR memory types - List of device bandwidths
- SDRAM latencySDRAM latencySDRAM latency refers to delays in transmitting data between the CPU and SDRAM. SDRAM latency is often measured in memory bus clock cycles. However, the CPU operates faster than the memory, so it must wait while the proper segment of memory is located and read, before the data can be sent back...