Synchronous dynamic random access memory
Encyclopedia
Synchronous dynamic random access memory (SDRAM) is dynamic random access memory
(DRAM) that is synchronized with the system bus
. Classic DRAM has an asynchronous interface, which means that it responds as quickly as possible to changes in control inputs. SDRAM has a synchronous interface, meaning that it waits for a clock signal
before responding to control inputs and is therefore synchronized with the computer's system bus. The clock is used to drive an internal finite state machine
that pipelines incoming instructions. This allows the chip to have a more complex pattern of operation than an asynchronous DRAM, enabling higher speeds.
Pipelining means that the chip can accept a new instruction before it has finished processing the previous one. In a pipelined write, the write command can be immediately followed by another instruction without waiting for the data to be written to the memory array. In a pipelined read, the requested data appears after a fixed number of clock pulses after the read instruction, cycles during which additional instructions can be sent. (This delay is called the latency
and is an important parameter to consider when purchasing SDRAM for a computer.)
SDRAM is widely used in computer
s; from the original SDRAM, further generations of DDR (or DDR1) and then DDR2 and DDR3 have entered the mass market
, with DDR4 currently being designed and anticipated to be available in 2015.
Although the concept of synchronous DRAM
has been known since at least the 1970s and was used with early Intel processors, it was only in 1993 that SDRAM began its path to universal acceptance in the electronics industry. In 1993, Samsung introduced its KM48SL2000 synchronous DRAM, and by 2000, SDRAM had replaced virtually all other types of DRAM
in modern computers, because of its greater performance.
SDRAM latency
is not inherently lower (faster) than asynchronous DRAM. Indeed, early SDRAM was somewhat slower than contemporaneous burst EDO DRAM due to the additional logic. The benefits of SDRAM's internal buffering come from its ability to interleave operations to multiple banks of memory, thereby increasing effective bandwidth
.
Today, virtually all SDRAM is manufactured in compliance with standards established by JEDEC
, an electronics industry association that adopts open standards to facilitate interoperability of electronic components. JEDEC formally adopted its first SDRAM standard in 1993 and subsequently adopted other SDRAM standards, including those for DDR
, DDR2
and DDR3 SDRAM
.
SDRAM is also available in registered
varieties, for systems that require greater scalability such as server
s and workstations.
, 168-pin SDRAM DIMM
s are not used in new PC systems, and 184-pin DDR memory has been mostly superseded. DDR2 SDRAM is the most common type used with new PCs, and DDR3 motherboards and memory are widely available, and less expensive than still-popular DDR2 products.
Today, the world's largest manufacturers of SDRAM include: Samsung Electronics
, Panasonic
, Micron Technology
, and Hynix
.
Another limit is the CAS latency
, the time between supplying a column address and receiving the corresponding data. Again, this has remained relatively constant at 10–15 ns through the last few generations of DDR SDRAM.
In operation, CAS latency is a specific number of clock cycles programmed into the SDRAM's mode register and expected by the DRAM controller. Any value may be programmed, but the SDRAM will not operate correctly if it is too low. At higher clock rates, the useful CAS latency in clock cycles naturally increases. 10–15 ns is 2–3 cycles (CL2–3) of the 200 MHz clock of DDR-400 SDRAM, CL4-6 for DDR2-800, and CL8-12 for DDR3-1600. Slower clock cycles will naturally allow lower numbers of CAS latency cycles.
SDRAM modules have their own timing specifications, which may be slower than those of the chips on the module. When 100 MHz SDRAM chips first appeared, some manufacturers sold "100 MHz" modules that could not reliably operate at that clock rate. In response, Intel published the PC100
standard, which outlines requirements and guidelines for producing a memory module that can operate reliably at 100 MHz. This standard was widely influential, and the term "PC100" quickly became a common identifier for 100 MHz SDRAM modules, and modules are now commonly designated with "PC"-prefixed numbers (PC66
, PC100
or PC133
- although the actual meaning of the numbers has changed).
Originally simply known as SDRAM, single data rate SDRAM can accept one command and transfer one word of data per clock cycle. Typical clock frequencies are 100 and 133 MHz. Chips are made with a variety of data bus sizes (most commonly 4, 8 or 16 bits), but chips are generally assembled into 168-pin DIMM
s that read or write 64 (non-ECC) or 72 (ECC
) bits at a time.
Use of the data bus is intricate and thus requires a complex DRAM controller circuit. This is because data written to the DRAM must be presented in the same cycle as the write command, but reads produce output 2 or 3 cycles after the read command. The DRAM controller must ensure that the data bus is never required for a read and a write at the same time.
Typical SDR SDRAM clock rates are 66, 100, and 133 MHz (periods of 15, 10, and 7.5 ns). Clock rates up to 150 MHz were available for performance enthusiasts.
, which are sampled on the rising edge of the clock:
SDRAM devices are internally divided into 2 or 4 independent internal data banks. One or two bank address inputs (BA0 and BA1) select which bank a command is directed toward.
Many commands also use an address presented on the address input pins. Some commands, which either do not use an address, or present a column address, also use A10 to select variants.
The commands understood are as follows:
The various DDRx SDRAM standards use essentially the same commands, with minor additions. Additional mode registers are distinguished using the bank address bits, and a third bank address bit is added.
SDRAM DIMM (which contains 512 MiB = = 536,870,912 bytes exactly) might be made of 8 or 9 SDRAM chips, each containing 512 Mbit
of storage, and each one contributing 8 bits to the DIMM's 64- or 72-bit width. A typical 512 Mbit SDRAM chip internally contains 4 independent 16 Mbyte memory banks. Each bank is an array of 8,192 rows of 16,384 bits each. A bank is either idle, active, or changing from one to the other.
The Active command activates an idle bank. It presents a 2-bit bank address (BA0 BA1) and a 13-bit row address (A0 A12), and causes a read of that row into the bank's array of all 16,384 column sense amplifiers. This is also known as "opening" the row. This operation has the side effect of refresh
ing the dynamic (capacitive) memory storage cells of that row.
Once the row has been activated or "opened", Read and Write commands are possible to that row. Activation requires a minimum amount of time, called the row-to-column delay, or tRCD before reads or writes to it may occur. This time, rounded up to the next multiple of the clock period, specifies the minimum number of wait cycles between an Active command, and a Read or Write command. During these wait cycles, additional commands may be sent to other banks; because each bank operates completely independently.
Both Read and Write commands require a column address. Because each chip accesses 8 bits of data at a time, there are 2048 possible column addresses thus requiring only 11 address lines (A0 A9, A11).
When a Read command is issued, the SDRAM will produce the corresponding output data on the DQ lines in time for the rising edge of the clock 2 or 3 clock cycles later (depending on the configured CAS latency). Subsequent words of the burst will be produced in time for subsequent rising clock edges.
A Write command is accompanied by the data to be written driven on to the DQ lines during the same rising clock edge. It is the duty of the memory controller to ensure that the SDRAM is not driving read data on to the DQ lines at the same time that it needs to drive write data on to those lines. This can be done by waiting until a read burst has finished, by terminating a read burst, or by using the DQM control line.
When the memory controller needs to access a different row, it must first return that bank's sense amplifiers to an idle state, ready to sense the next row. This is known as a "precharge" operation, or "closing" the row. A precharge may be commanded explicitly, or it may be performed automatically at the conclusion of a read or write operation. Again, there is a minimum time, the row precharge delay, tRP, which must elapse before that bank is fully idle and it may receive another activate command.
Although refreshing a row is an automatic side effect of activating it, there is a minimum time for this to happen, which requires a minimum row access time tRAS delay between an Active command opening a row, and the corresponding precharge command closing it. This limit is usually dwarfed by desired read and write commands to the row, so its value has little effect on typical performance.
The load mode register command requires that all banks be idle, and a delay afterward for the changes to take effect.
The auto refresh command also requires that all banks be idle, and takes a refresh cycle time tRFC to return the chip to the idle state. (This time is usually equal to tRCD+tRP.)
The only other command that is permitted on an idle bank is the active command. This takes, as mentioned above, tRCD before the row is fully open and can accept read and write commands.
When a bank is open, there are four commands permitted: read, write, burst terminate, and precharge. Read and write commands begin bursts, which can be interrupted by following commands.
If the command issued on cycle 2 were burst terminate, or a precharge of the active bank, then no output would be generated during cycle 5.
Although the interrupting read may be to any active bank, a precharge command will only interrupt the read burst if it is to the same bank or all banks; a precharge command to a different bank will not interrupt a read burst.
To interrupt a read burst by a write command is possible, but more difficult. It can be done, if the DQM signal is used to suppress output from the SDRAM so that the memory controller may drive data over the DQ lines to the SDRAM in time for the write operation. Because the effects of DQM on read data are delayed by 2 cycles, but the effects of DQM on write data are immediate, DQM must be raised (to mask the read data) beginning at least two cycles before write command, but must be lowered for the cycle of the write command (assuming you want the write command to have an effect).
Doing this in only two clock cycles requires careful coordination between the time the SDRAM takes to turn off its output on a clock edge and the time the data must be supplied as input to the SDRAM for the write on the following clock edge. If the clock frequency is too high to allow sufficient time, three cycles may be required.
If the read command includes auto-precharge, the precharge begins the same cycle as the interrupting command.
will generally access memory in units of cache lines. To transfer a 64-byte cache line requires 8 consecutive accesses to a 64-bit DIMM, which can all be triggered by a single read or write command by configuring the SDRAM chips, using the mode register, to perform 8-word bursts.
A cache line fetch is typically triggered by a read from a particular address, and SDRAM allows the "critical word" of the cache line to be transferred first. ("Word" here refers to the width of the SDRAM chip or DIMM, which is 64 bits for a typical DIMM.) SDRAM chips support two possible conventions for the ordering of the remaining words in the cache line.
Bursts always access an aligned block of BL consecutive words beginning on a multiple of BL. So, for example, a 4-word burst access to any column address from 4 to 7 will return words 4 7. The ordering, however, depends on the requested address, and the configured burst type option: sequential or interleaved. Typically, a memory controller will require one or the other.
When the burst length is 1 or 2, the burst type does not matter. For a burst length of 1, the requested word is the only word accessed. For a burst length of 2, the requested word is accessed first, and the other word in the aligned block is accessed second. This is the following word if an even address was specified, and the previous word if an odd address was specified.
For the sequential burst mode, later words are accessed in increasing address order, wrapping back to the start of the block when the end is reached. So, for example, for a burst length of 4, and a requested column address of 5, the words would be accessed in the order 5-6-7-4. If the burst length were 8, the access order would be 5-6-7-0-1-2-3-4. This is done by adding a counter to the column address, and ignoring carries past the burst length.
The interleaved burst mode computes the address using an exclusive or operation between the counter and the address. Using the same starting address of 5, a 4-word burst would return words in the order 5-4-7-6. An 8-word burst would be 5-4-7-6-1-0-3-2. Although more confusing to humans, this can be easier to implement in hardware, and is preferred by Intel microprocessors.
If the requested column address is at the start of a block, both burst modes return data in the same sequential sequence 0-1-2-3-4-5-6-7. The difference only matters if fetching a cache line from memory in critical-word-first order.
The bits are M9 through M0, presented on address lines A9 through A0 during a load mode register cycle.
Later (double data rate) SDRAM standards use more mode register bits, and provide additional extended mode registers. The register number is encoded on the bank address pins during the load mode register cycle. For example, DDR2 SDRAM has a 13-bit mode register, a 13-bit EMR1, and uses 5 bits in EMR2.
If CKE is lowered while the SDRAM is performing operations, it simply "freezes" in place until CKE is raised again.
If the SDRAM is idle (all banks precharged, no commands in progress) when CKE is lowered, the SDRAM automatically enters power-down mode, consuming minimal power until CKE is raised again. This must not last longer than the maximum refresh interval tREF, or memory contents may be lost. It is legal to stop the clock entirely during this time for additional power savings.
Finally, if CKE is lowered at the same time as an auto-refresh command is sent to the SDRAM, the SDRAM enters self-refresh mode. This is like power down, but the SDRAM uses an on-chip timer to generate internal refresh cycles as necessary. The clock may be stopped during this time. While self-refresh mode consumes slightly more power than power-down mode, it allows the memory controller to be disabled entirely, which commonly more than makes up the difference.
SDRAM designed for battery-powered devices offers some additional power-saving options. One is temperature-dependent refresh; an on-chip temperature sensor reduces the refresh rate at lower temperatures, rather than always running it at the worst-case rate. Another is selective refresh, which limits self-refresh to a portion of the DRAM array. The fraction which is refreshed is configured using an extended mode register. The third, implemented in Mobile DDR
(LPDDR) and LPDDR2 is "deep power down" mode, which invalidates the memory and requires a full reinitialization to exit from. This is activated by sending a "burst terminate" command while lowering CKE.
interface was developed. This uses the same commands, accepted once per cycle, but reads or writes two words of data per clock cycle. The DDR interface accomplishes this by reading and writing data on both the rising and falling edges of the clock signal. In addition, some minor changes to the SDR interface timing were made in hindsight, and the supply voltage was reduced from 3.3 to 2.5 V. As a result, DDR SDRAM is not backwards compatible with SDR SDRAM.
DDR SDRAM (sometimes called DDR1 for greater clarity) doubles the minimum read or write unit; every access refers to at least two consecutive words.
Typical DDR SDRAM clock rates are 133, 166 and 200 MHz (7.5, 6, and 5 ns/cycle), generally described as DDR-266, DDR-333 and DDR-400 (3.75, 3, and 2.5 ns per beat). Corresponding 184-pin DIMMs are known as PC-2100, PC-2700 and PC-3200. Performance up to DDR-550 (PC-4400) is available for a price.
Typical DDR2 SDRAM clock rates are 200, 266, 333 or 400 MHz (periods of 5, 3.75, 3 and 2.5 ns), generally described as DDR2-400, DDR2-533, DDR2-667 and DDR2-800 (periods of 2.5, 1.875, 1.5 and 1.25 ns). Corresponding 240-pin DIMMS are known as PC2-3200 through PC2-6400. DDR2 SDRAM is now available at a clock rate of 533 MHz generally described as DDR2-1066 and the corresponding DIMMs are known as PC2-8500 (also named PC2-8600 depending on the manufacturer). Performance up to DDR2-1250 (PC2-10000) is available for a price.
Note that because internal operations are at 1/2 the clock rate, DDR2-400 memory (internal clock rate 100 MHz) has somewhat higher latency than DDR-400 (internal clock rate 200 MHz).
Again, with every doubling, the downside is the increased latency
. As with all DDR SDRAM generations, commands are still restricted to one clock edge and command latencies are given in terms of clock cycles, which are half the speed of the usually quoted transfer rate (a CAS latency
of 8 with DDR3-800 is 8/(400 MHz) = 20 ns, exactly the same latency of CAS2 on PC100
SDR SDRAM).
DDR3 memory chips are being made commercially, and computer systems are available that use them as of the second half of 2007, with expected significant usage in 2008. Initial clock rates were 400 and 533 MHz, which are described as DDR3-800 and DDR3-1066 (PC3-6400 and PC3-8500 modules), but 667 and 800 MHz, described as DDR3-1333 and DDR3-1600 (PC3-10600 and PC3-12800 modules) are now common. Performance up to DDR3-2200 (PC3 17600 modules) are available for a price.
. It was revealed at the Intel Developer Forum
in San Francisco in 2008, and is due to be released to market during 2011. The timing has varied considerably during its development - it was originally expected to be released in 2012, and later (during 2010) expected to be released in 2015, before samples were announced in early 2011 and manufacturers began to announce that commercial production and release to market was anticipated in 2012. DDR4 is expected to reach mass market adoption around 2015, which is comparable with the approximately 5 years taken for DDR3 to achieve mass market transition over DDR2.
The new chips are expected to run at 1.2 V
or less, versus the 1.5 V of DDR3 chips, and have in excess of 2 billion data transfers per second. They are expected to be introduced at frequency rates of 2133 MHz, estimated to rise to a potential 4266 MHz and lowered voltage of 1.05 V by 2013.
In February 2009, Samsung
validated 40 nm DRAM chips, considered a "significant step" towards DDR4 development since as of 2009, current DRAM chips were only beginning to migrate to a 50 nm process. In January 2011, Samsung
announced the completion and release for testing of a 30 nm 2 GB DDR4 DRAM module. It has a maximum bandwidth of 2.13 Gbit/s at 1.2 V, uses pseudo open drain technology and draws 40% less power than an equivalent DDR3 module.
was a proprietary technology that competed against DDR. Its relatively high price and disappointing performance (resulting from high latencies and a narrow 16-bit data channel versus DDR's 64 bit channel) caused it to lose the race to succeed SDR DRAM.
and does not require licensing fees. The specifications called for a 64-bit bus running at a 200 MHz clock frequency. This is achieved by all signals being on the same line and thereby avoiding the synchronization time of multiple lines. Like DDR SDRAM
, SLDRAM uses an double-pumped bus, giving it an effective speed of 400 MT/s.
, but released as an open standard with no licensing fees. VCM creates a state in which the various system processes can be assigned their own virtual channel, thus increasing the overall system efficiency by avoiding the need to have processes share buffer space. This is accomplished by creating different "blocks" of memory, allowing each individual memory block to interface separately with the memory controller and have its own buffer space. VCM has higher performance than SDRAM because it has significantly lower latencies. The technology was a potential competitor of RDRAM
because VCM was not nearly as expensive as RDRAM was. A Virtual Channel Memory (VCM) module is mechanically and electrically compatible with standard SDRAM, but must be recognized by the memory controller
. Few motherboards were ever produced with VCM support.
Dynamic random access memory
Dynamic random-access memory is a type of random-access memory that stores each bit of data in a separate capacitor within an integrated circuit. The capacitor can be either charged or discharged; these two states are taken to represent the two values of a bit, conventionally called 0 and 1...
(DRAM) that is synchronized with the system bus
System bus
A system bus is a single computer bus that connects the major components of a computer system. The technique was developed to reduce costs and improve modularity....
. Classic DRAM has an asynchronous interface, which means that it responds as quickly as possible to changes in control inputs. SDRAM has a synchronous interface, meaning that it waits for a clock signal
Clock signal
In electronics and especially synchronous digital circuits, a clock signal is a particular type of signal that oscillates between a high and a low state and is utilized like a metronome to coordinate actions of circuits...
before responding to control inputs and is therefore synchronized with the computer's system bus. The clock is used to drive an internal finite state machine
Finite state machine
A finite-state machine or finite-state automaton , or simply a state machine, is a mathematical model used to design computer programs and digital logic circuits. It is conceived as an abstract machine that can be in one of a finite number of states...
that pipelines incoming instructions. This allows the chip to have a more complex pattern of operation than an asynchronous DRAM, enabling higher speeds.
Pipelining means that the chip can accept a new instruction before it has finished processing the previous one. In a pipelined write, the write command can be immediately followed by another instruction without waiting for the data to be written to the memory array. In a pipelined read, the requested data appears after a fixed number of clock pulses after the read instruction, cycles during which additional instructions can be sent. (This delay is called the latency
SDRAM latency
SDRAM latency refers to delays in transmitting data between the CPU and SDRAM. SDRAM latency is often measured in memory bus clock cycles. However, the CPU operates faster than the memory, so it must wait while the proper segment of memory is located and read, before the data can be sent back...
and is an important parameter to consider when purchasing SDRAM for a computer.)
SDRAM is widely used in computer
Computer
A computer is a programmable machine designed to sequentially and automatically carry out a sequence of arithmetic or logical operations. The particular sequence of operations can be changed readily, allowing the computer to solve more than one kind of problem...
s; from the original SDRAM, further generations of DDR (or DDR1) and then DDR2 and DDR3 have entered the mass market
Mass market
The mass market is a general business term describing the largest group of consumers for a specified industry product. It is the opposite extreme of the term niche market.-General:...
, with DDR4 currently being designed and anticipated to be available in 2015.
SDRAM history
Dram
Dram or DRAM may refer to:As a unit of measure:* Dram , an imperial unit of mass and volume* Armenian dram, a monetary unit* Dirham, a unit of currency in several Arab nationsOther uses:...
has been known since at least the 1970s and was used with early Intel processors, it was only in 1993 that SDRAM began its path to universal acceptance in the electronics industry. In 1993, Samsung introduced its KM48SL2000 synchronous DRAM, and by 2000, SDRAM had replaced virtually all other types of DRAM
Dram
Dram or DRAM may refer to:As a unit of measure:* Dram , an imperial unit of mass and volume* Armenian dram, a monetary unit* Dirham, a unit of currency in several Arab nationsOther uses:...
in modern computers, because of its greater performance.
SDRAM latency
SDRAM latency
SDRAM latency refers to delays in transmitting data between the CPU and SDRAM. SDRAM latency is often measured in memory bus clock cycles. However, the CPU operates faster than the memory, so it must wait while the proper segment of memory is located and read, before the data can be sent back...
is not inherently lower (faster) than asynchronous DRAM. Indeed, early SDRAM was somewhat slower than contemporaneous burst EDO DRAM due to the additional logic. The benefits of SDRAM's internal buffering come from its ability to interleave operations to multiple banks of memory, thereby increasing effective bandwidth
Bandwidth (computing)
In computer networking and computer science, bandwidth, network bandwidth, data bandwidth, or digital bandwidth is a measure of available or consumed data communication resources expressed in bits/second or multiples of it .Note that in textbooks on wireless communications, modem data transmission,...
.
Today, virtually all SDRAM is manufactured in compliance with standards established by JEDEC
JEDEC
The JEDEC Solid State Technology Association, formerly known as the Joint Electron Devices Engineering Council , is an independent semiconductor engineering trade organization and standardization body...
, an electronics industry association that adopts open standards to facilitate interoperability of electronic components. JEDEC formally adopted its first SDRAM standard in 1993 and subsequently adopted other SDRAM standards, including those for DDR
DDR SDRAM
Double data rate synchronous dynamic random access memory is a class of memory integrated circuits used in computers. DDR SDRAM has been superseded by DDR2 SDRAM and DDR3 SDRAM, neither of which are either forward or backward compatible with DDR SDRAM, meaning that DDR2 or DDR3 memory modules...
, DDR2
DDR2 SDRAM
DDR2 SDRAM is a double data rate synchronous dynamic random-access memory interface. It supersedes the original DDR SDRAM specification and has itself been superseded by DDR3 SDRAM...
and DDR3 SDRAM
DDR3 SDRAM
In computing, DDR3 SDRAM, an abbreviation for double data rate type three synchronous dynamic random access memory, is a modern kind of dynamic random access memory with a high bandwidth interface. It is one of several variants of DRAM and associated interface techniques used since the early 1970s...
.
SDRAM is also available in registered
Registered memory
Registered memory modules have a register between the DRAM modules and the system's memory controller. They place less electrical load on the memory controller and allow single systems to remain stable with more memory modules than they would have otherwise...
varieties, for systems that require greater scalability such as server
Server (computing)
In the context of client-server architecture, a server is a computer program running to serve the requests of other programs, the "clients". Thus, the "server" performs some computational task on behalf of "clients"...
s and workstations.
, 168-pin SDRAM DIMM
DIMM
A DIMM or dual in-line memory module, comprises a series of dynamic random-access memory integrated circuits. These modules are mounted on a printed circuit board and designed for use in personal computers, workstations and servers...
s are not used in new PC systems, and 184-pin DDR memory has been mostly superseded. DDR2 SDRAM is the most common type used with new PCs, and DDR3 motherboards and memory are widely available, and less expensive than still-popular DDR2 products.
Today, the world's largest manufacturers of SDRAM include: Samsung Electronics
Samsung Electronics
Samsung Electronics is a South Korean multinational electronics and information technology company headquartered in Samsung Town, Seoul...
, Panasonic
Panasonic
Panasonic is an international brand name for Japanese electric products manufacturer Panasonic Corporation, which was formerly known as Matsushita Electric Industrial Co., Ltd...
, Micron Technology
Micron Technology
Micron Technology, Inc. is an American multinational corporation based in Boise, Idaho, USA, best known for producing many forms of semiconductor devices. This includes DRAM, SDRAM, flash memory, SSD and CMOS image sensing chips. Consumers may be more familiar with its consumer brand Crucial...
, and Hynix
Hynix
Hynix Semiconductor Inc. chips and flash memory chips. Founded in 1983, Hynix is the world's second-largest memory chipmaker, the largest being Samsung Electronics. Formerly known as Hyundai Electronics, the company has manufacturing sites in Korea, the U.S., China and Taiwan...
.
SDRAM timing
There are several limits on DRAM performance. Most noted is the read cycle time, the time between successive read operations to an open row. This time decreased from 10 ns for 100 MHz SDRAM to 5 ns for DDR-400, but has remained relatively unchanged through DDR2-800 and DDR3-1600 generations. However, by operating the interface circuitry at increasingly higher multiples of the fundamental read rate, the achievable bandwidth has increased rapidly.Another limit is the CAS latency
CAS Latency
Column Address Strobe latency, or CL, is the delay time between the moment a memory controller tells the memory module to access a particular memory column on a RAM memory module, and the moment the data from given array location is available on the module's output pins...
, the time between supplying a column address and receiving the corresponding data. Again, this has remained relatively constant at 10–15 ns through the last few generations of DDR SDRAM.
In operation, CAS latency is a specific number of clock cycles programmed into the SDRAM's mode register and expected by the DRAM controller. Any value may be programmed, but the SDRAM will not operate correctly if it is too low. At higher clock rates, the useful CAS latency in clock cycles naturally increases. 10–15 ns is 2–3 cycles (CL2–3) of the 200 MHz clock of DDR-400 SDRAM, CL4-6 for DDR2-800, and CL8-12 for DDR3-1600. Slower clock cycles will naturally allow lower numbers of CAS latency cycles.
SDRAM modules have their own timing specifications, which may be slower than those of the chips on the module. When 100 MHz SDRAM chips first appeared, some manufacturers sold "100 MHz" modules that could not reliably operate at that clock rate. In response, Intel published the PC100
PC100
PC100 is a standard for internal removable computer random access memory, defined by the JEDEC. PC100 refers to Synchronous DRAM operating at a clock frequency of 100 MHz, on a 64-bit-wide bus, at a voltage of 3.3 V. PC100 is available in 168-pin DIMM and 144-pin SO-DIMM form factors...
standard, which outlines requirements and guidelines for producing a memory module that can operate reliably at 100 MHz. This standard was widely influential, and the term "PC100" quickly became a common identifier for 100 MHz SDRAM modules, and modules are now commonly designated with "PC"-prefixed numbers (PC66
PC66
PC66 refers to internal removable computer memory standard defined by the JEDEC. PC66 is Synchronous DRAM operating at a clock frequency of 66.66 MHz, on a 64-bit bus, at a voltage of 3.3 V. PC66 is available in 168 pin DIMM and 144 pin SO-DIMM form factors. The theoretical bandwidth is...
, PC100
PC100
PC100 is a standard for internal removable computer random access memory, defined by the JEDEC. PC100 refers to Synchronous DRAM operating at a clock frequency of 100 MHz, on a 64-bit-wide bus, at a voltage of 3.3 V. PC100 is available in 168-pin DIMM and 144-pin SO-DIMM form factors...
or PC133
PC133
PC133 is a computer memory standard defined by the JEDEC. PC133 refers to Synchronous DRAM operating at a clock frequency of 133 MHz, on a 64-bit-wide bus, at a voltage of 3.3 V. PC133 is available in 168 pin DIMM and 144 pin SO-DIMM form factors...
- although the actual meaning of the numbers has changed).
SDR SDRAM
DIMM
A DIMM or dual in-line memory module, comprises a series of dynamic random-access memory integrated circuits. These modules are mounted on a printed circuit board and designed for use in personal computers, workstations and servers...
s that read or write 64 (non-ECC) or 72 (ECC
ECC memory
Error-correcting code memory is a type of computer data storage that can detect and correct the more common kinds of internal data corruption...
) bits at a time.
Use of the data bus is intricate and thus requires a complex DRAM controller circuit. This is because data written to the DRAM must be presented in the same cycle as the write command, but reads produce output 2 or 3 cycles after the read command. The DRAM controller must ensure that the data bus is never required for a read and a write at the same time.
Typical SDR SDRAM clock rates are 66, 100, and 133 MHz (periods of 15, 10, and 7.5 ns). Clock rates up to 150 MHz were available for performance enthusiasts.
SDRAM control signals
All commands are timed relative to the rising edge of a clock signal. In addition to the clock, there are 6 control signals, mostly active lowLogic level
In digital circuits, a logic level is one of a finite number of states that a signal can have. Logic levels are usually represented by the voltage difference between the signal and ground , although other standards exist...
, which are sampled on the rising edge of the clock:
- CKE Clock Enable. When this signal is low, the chip behaves as if the clock has stopped. No commands are interpreted and command latency times do not elapse. The state of other control lines is not relevant. The effect of this signal is actually delayed by one clock cycle. That is, the current clock cycle proceeds as usual, but the following clock cycle is ignored, except for testing the CKE input again. Normal operations resume on the rising edge of the clock after the one where CKE is sampled high.
Put another way, all other chip operations are timed relative to the rising edge of a masked clock. The masked clock is the logical AND of the input clock and the state of the CKE signal during the previous rising edge of the input clock. - /CS Chip Select. When this signal is high, the chip ignores all other inputs (except for CKE), and acts as if a NOP command is received.
- DQM Data Mask. (The letter Q appears because, following digital logic conventions, the data lines are known as "DQ" lines.) When high, these signals suppress data I/O. When accompanying write data, the data is not actually written to the DRAM. When asserted high two cycles before a read cycle, the read data is not output from the chip. There is one DQM line per 8 bits on a x16 memory chip or DIMM.
- /RAS Row Address Strobe. Despite the name, this is not a strobe, but rather simply a command bit. Along with /CAS and /WE, this selects one of 8 commands.
- /CAS Column Address Strobe. Despite the name, this is not a strobe, but rather simply a command bit. Along with /RAS and /WE, this selects one of 8 commands.
- /WE Write enable. Along with /RAS and /CAS, this selects one of 8 commands. This generally distinguishes read-like commands from write-like commands.
SDRAM devices are internally divided into 2 or 4 independent internal data banks. One or two bank address inputs (BA0 and BA1) select which bank a command is directed toward.
Many commands also use an address presented on the address input pins. Some commands, which either do not use an address, or present a column address, also use A10 to select variants.
The commands understood are as follows:
| /CS | /RAS | /CAS | /WE | BAn | A10 | An | Command |
|---|---|---|---|---|---|---|---|
| H | x | x | x | x | x | x | Command inhibit (No operation) |
| L | H | H | H | x | x | x | No operation |
| L | H | H | L | x | x | x | Burst Terminate: stop a burst read or burst write in progress. |
| L | H | L | H | bank | L | column | Read: Read a burst of data from the currently active row. |
| L | H | L | H | bank | H | column | Read with auto precharge: As above, and precharge (close row) when done. |
| L | H | L | L | bank | L | column | Write: Write a burst of data to the currently active row. |
| L | H | L | L | bank | H | column | Write with auto precharge: As above, and precharge (close row) when done. |
| L | L | H | H | bank | row | Active (activate): open a row for Read and Write commands. | |
| L | L | H | L | bank | L | x | Precharge: Deactivate current row of selected bank. |
| L | L | H | L | x | H | x | Precharge all: Deactivate current row of all banks. |
| L | L | L | H | x | x | x | Auto refresh: Refresh one row of each bank, using an internal counter. All banks must be precharged. |
| L | L | L | L | 0 0 | mode | Load mode register: A0 through A9 are loaded to configure the DRAM chip. The most significant settings are CAS latency (2 or 3 cycles) and burst length (1, 2, 4 or 8 cycles) |
|
The various DDRx SDRAM standards use essentially the same commands, with minor additions. Additional mode registers are distinguished using the bank address bits, and a third bank address bit is added.
SDRAM operation
A 512 MBMegabyte
The megabyte is a multiple of the unit byte for digital information storage or transmission with two different values depending on context: bytes generally for computer memory; and one million bytes generally for computer storage. The IEEE Standards Board has decided that "Mega will mean 1 000...
SDRAM DIMM (which contains 512 MiB = = 536,870,912 bytes exactly) might be made of 8 or 9 SDRAM chips, each containing 512 Mbit
Megabit
The megabit is a multiple of the unit bit for digital information or computer storage. The prefix mega is defined in the International System of Units as a multiplier of 106 , and therefore...
of storage, and each one contributing 8 bits to the DIMM's 64- or 72-bit width. A typical 512 Mbit SDRAM chip internally contains 4 independent 16 Mbyte memory banks. Each bank is an array of 8,192 rows of 16,384 bits each. A bank is either idle, active, or changing from one to the other.
The Active command activates an idle bank. It presents a 2-bit bank address (BA0 BA1) and a 13-bit row address (A0 A12), and causes a read of that row into the bank's array of all 16,384 column sense amplifiers. This is also known as "opening" the row. This operation has the side effect of refresh
Memory refresh
Memory refresh is the process of periodically reading information from an area of computer memory, and immediately rewriting the read information to the same area with no modifications. Each memory refresh cycle refreshes a succeeding area of memory. Memory refresh is most often associated with...
ing the dynamic (capacitive) memory storage cells of that row.
Once the row has been activated or "opened", Read and Write commands are possible to that row. Activation requires a minimum amount of time, called the row-to-column delay, or tRCD before reads or writes to it may occur. This time, rounded up to the next multiple of the clock period, specifies the minimum number of wait cycles between an Active command, and a Read or Write command. During these wait cycles, additional commands may be sent to other banks; because each bank operates completely independently.
Both Read and Write commands require a column address. Because each chip accesses 8 bits of data at a time, there are 2048 possible column addresses thus requiring only 11 address lines (A0 A9, A11).
When a Read command is issued, the SDRAM will produce the corresponding output data on the DQ lines in time for the rising edge of the clock 2 or 3 clock cycles later (depending on the configured CAS latency). Subsequent words of the burst will be produced in time for subsequent rising clock edges.
A Write command is accompanied by the data to be written driven on to the DQ lines during the same rising clock edge. It is the duty of the memory controller to ensure that the SDRAM is not driving read data on to the DQ lines at the same time that it needs to drive write data on to those lines. This can be done by waiting until a read burst has finished, by terminating a read burst, or by using the DQM control line.
When the memory controller needs to access a different row, it must first return that bank's sense amplifiers to an idle state, ready to sense the next row. This is known as a "precharge" operation, or "closing" the row. A precharge may be commanded explicitly, or it may be performed automatically at the conclusion of a read or write operation. Again, there is a minimum time, the row precharge delay, tRP, which must elapse before that bank is fully idle and it may receive another activate command.
Although refreshing a row is an automatic side effect of activating it, there is a minimum time for this to happen, which requires a minimum row access time tRAS delay between an Active command opening a row, and the corresponding precharge command closing it. This limit is usually dwarfed by desired read and write commands to the row, so its value has little effect on typical performance.
Command interactions
The no operation command is always permitted.The load mode register command requires that all banks be idle, and a delay afterward for the changes to take effect.
The auto refresh command also requires that all banks be idle, and takes a refresh cycle time tRFC to return the chip to the idle state. (This time is usually equal to tRCD+tRP.)
The only other command that is permitted on an idle bank is the active command. This takes, as mentioned above, tRCD before the row is fully open and can accept read and write commands.
When a bank is open, there are four commands permitted: read, write, burst terminate, and precharge. Read and write commands begin bursts, which can be interrupted by following commands.
Interrupting a read burst
A read, burst terminate, or precharge command may be issued at any time after a read command, and will interrupt the read burst after the configured CAS latency. So if a read command is issued on cycle 0, another read command is issued on cycle 2, and the CAS latency is 3, then the first read command will begin bursting data out during cycles 3 and 4, then the results from the second read command will appear beginning with cycle 5.If the command issued on cycle 2 were burst terminate, or a precharge of the active bank, then no output would be generated during cycle 5.
Although the interrupting read may be to any active bank, a precharge command will only interrupt the read burst if it is to the same bank or all banks; a precharge command to a different bank will not interrupt a read burst.
To interrupt a read burst by a write command is possible, but more difficult. It can be done, if the DQM signal is used to suppress output from the SDRAM so that the memory controller may drive data over the DQ lines to the SDRAM in time for the write operation. Because the effects of DQM on read data are delayed by 2 cycles, but the effects of DQM on write data are immediate, DQM must be raised (to mask the read data) beginning at least two cycles before write command, but must be lowered for the cycle of the write command (assuming you want the write command to have an effect).
Doing this in only two clock cycles requires careful coordination between the time the SDRAM takes to turn off its output on a clock edge and the time the data must be supplied as input to the SDRAM for the write on the following clock edge. If the clock frequency is too high to allow sufficient time, three cycles may be required.
If the read command includes auto-precharge, the precharge begins the same cycle as the interrupting command.
SDRAM burst ordering
A modern microprocessor with a cacheCPU cache
A CPU cache is a cache used by the central processing unit of a computer to reduce the average time to access memory. The cache is a smaller, faster memory which stores copies of the data from the most frequently used main memory locations...
will generally access memory in units of cache lines. To transfer a 64-byte cache line requires 8 consecutive accesses to a 64-bit DIMM, which can all be triggered by a single read or write command by configuring the SDRAM chips, using the mode register, to perform 8-word bursts.
A cache line fetch is typically triggered by a read from a particular address, and SDRAM allows the "critical word" of the cache line to be transferred first. ("Word" here refers to the width of the SDRAM chip or DIMM, which is 64 bits for a typical DIMM.) SDRAM chips support two possible conventions for the ordering of the remaining words in the cache line.
Bursts always access an aligned block of BL consecutive words beginning on a multiple of BL. So, for example, a 4-word burst access to any column address from 4 to 7 will return words 4 7. The ordering, however, depends on the requested address, and the configured burst type option: sequential or interleaved. Typically, a memory controller will require one or the other.
When the burst length is 1 or 2, the burst type does not matter. For a burst length of 1, the requested word is the only word accessed. For a burst length of 2, the requested word is accessed first, and the other word in the aligned block is accessed second. This is the following word if an even address was specified, and the previous word if an odd address was specified.
For the sequential burst mode, later words are accessed in increasing address order, wrapping back to the start of the block when the end is reached. So, for example, for a burst length of 4, and a requested column address of 5, the words would be accessed in the order 5-6-7-4. If the burst length were 8, the access order would be 5-6-7-0-1-2-3-4. This is done by adding a counter to the column address, and ignoring carries past the burst length.
The interleaved burst mode computes the address using an exclusive or operation between the counter and the address. Using the same starting address of 5, a 4-word burst would return words in the order 5-4-7-6. An 8-word burst would be 5-4-7-6-1-0-3-2. Although more confusing to humans, this can be easier to implement in hardware, and is preferred by Intel microprocessors.
If the requested column address is at the start of a block, both burst modes return data in the same sequential sequence 0-1-2-3-4-5-6-7. The difference only matters if fetching a cache line from memory in critical-word-first order.
SDRAM mode register
Single data rate SDRAM has a single 10-bit programmable mode register. Later double-data-rate SDRAM standards add additional mode registers, addressed using the bank address pins. For SDR SDRAM, the bank address pins and address lines A10 and above are ignored, but should be zero during a mode register write.The bits are M9 through M0, presented on address lines A9 through A0 during a load mode register cycle.
- M9: Write burst mode. If 0, writes use the read burst length and mode. If 1, all writes are non-burst (single location).
- M8, M7: Operating mode. Reserved, and must be 00.
- M6, M5, M4: CAS latency. Generally only 010 (CL2) and 011 (CL3) are legal. Specifies the number of cycles between a read command and data output from the chip. The chip has a fundamental limit on this value in nanoseconds; during initialization, the memory controller must use its knowledge of the clock frequency to translate that limit into cycles.
- M3: Burst type. 0 - requests sequential burst ordering, while 1 requests interleaved burst ordering.
- M2, M1, M0: Burst length. Values of 000, 001, 010 and 011 specify a burst size of 1, 2, 4 or 8 words, respectively. Each read (and write, if M9 is 0) will perform that many accesses, unless interrupted by a burst stop or other command. A value of 111 specifies a full-row burst. The burst will continue until interrupted. Full-row bursts are only permitted with the sequential burst type.
Later (double data rate) SDRAM standards use more mode register bits, and provide additional extended mode registers. The register number is encoded on the bank address pins during the load mode register cycle. For example, DDR2 SDRAM has a 13-bit mode register, a 13-bit EMR1, and uses 5 bits in EMR2.
Auto refresh
It is possible to refresh a RAM chip by opening and closing (activating and precharging) each row in each bank. However, to simplify the memory controller, SDRAM chips support an "auto refresh" command, which performs these operations to one row in each bank simultaneously. The SDRAM also maintains an internal counter, which iterates over all possible rows. The memory controller must simply issue a sufficient number of auto refresh commands (one per row, 4096 in the example we have been using) every refresh interval (tREF = 64 ms is a common value). All banks must be idle (closed, precharged) when this command is issued.Low power modes
As mentioned, the clock enable (CKE) input can be used to effectively stop the clock to an SDRAM. The CKE input is sampled each rising edge of the clock, and if it is low, the following rising edge of the clock is ignored for all purposes other than checking CKE. As long as CKE is low, it is permissible to change the clock rate, or even stop the clock entirely.If CKE is lowered while the SDRAM is performing operations, it simply "freezes" in place until CKE is raised again.
If the SDRAM is idle (all banks precharged, no commands in progress) when CKE is lowered, the SDRAM automatically enters power-down mode, consuming minimal power until CKE is raised again. This must not last longer than the maximum refresh interval tREF, or memory contents may be lost. It is legal to stop the clock entirely during this time for additional power savings.
Finally, if CKE is lowered at the same time as an auto-refresh command is sent to the SDRAM, the SDRAM enters self-refresh mode. This is like power down, but the SDRAM uses an on-chip timer to generate internal refresh cycles as necessary. The clock may be stopped during this time. While self-refresh mode consumes slightly more power than power-down mode, it allows the memory controller to be disabled entirely, which commonly more than makes up the difference.
SDRAM designed for battery-powered devices offers some additional power-saving options. One is temperature-dependent refresh; an on-chip temperature sensor reduces the refresh rate at lower temperatures, rather than always running it at the worst-case rate. Another is selective refresh, which limits self-refresh to a portion of the DRAM array. The fraction which is refreshed is configured using an extended mode register. The third, implemented in Mobile DDR
Mobile DDR
Mobile DDR is type of double data rate synchronous DRAM for mobile computers.-Original LPDDR:...
(LPDDR) and LPDDR2 is "deep power down" mode, which invalidates the memory and requires a full reinitialization to exit from. This is activated by sending a "burst terminate" command while lowering CKE.
SDRAM (synchronous DRAM)
This type of SDRAM is slower than the DDR variants, because only one word of data is transmitted per clock cycle (single data rate).DDR SDRAM (DDR1)
While the access latency of DRAM is fundamentally limited by the DRAM array, DRAM has very high potential bandwidth because each internal read is actually a row of many thousands of bits. To make more of this bandwidth available to users, a double data rateDouble data rate
In computing, a computer bus operating with double data rate transfers data on both the rising and falling edges of the clock signal. This is also known as double pumped, dual-pumped, and double transition....
interface was developed. This uses the same commands, accepted once per cycle, but reads or writes two words of data per clock cycle. The DDR interface accomplishes this by reading and writing data on both the rising and falling edges of the clock signal. In addition, some minor changes to the SDR interface timing were made in hindsight, and the supply voltage was reduced from 3.3 to 2.5 V. As a result, DDR SDRAM is not backwards compatible with SDR SDRAM.
DDR SDRAM (sometimes called DDR1 for greater clarity) doubles the minimum read or write unit; every access refers to at least two consecutive words.
Typical DDR SDRAM clock rates are 133, 166 and 200 MHz (7.5, 6, and 5 ns/cycle), generally described as DDR-266, DDR-333 and DDR-400 (3.75, 3, and 2.5 ns per beat). Corresponding 184-pin DIMMs are known as PC-2100, PC-2700 and PC-3200. Performance up to DDR-550 (PC-4400) is available for a price.
DDR2 SDRAM
DDR2 SDRAM is very similar to DDR SDRAM, but doubles the minimum read or write unit again, to 4 consecutive words. The bus protocol was also simplified to allow higher performance operation. (In particular, the "burst terminate" command is deleted.) This allows the bus rate of the SDRAM to be doubled without increasing the clock rate of internal RAM operations; instead, internal operations are performed in units 4 times as wide as SDRAM. Also, an extra bank address pin (BA2) was added to allow 8 banks on large RAM chips.Typical DDR2 SDRAM clock rates are 200, 266, 333 or 400 MHz (periods of 5, 3.75, 3 and 2.5 ns), generally described as DDR2-400, DDR2-533, DDR2-667 and DDR2-800 (periods of 2.5, 1.875, 1.5 and 1.25 ns). Corresponding 240-pin DIMMS are known as PC2-3200 through PC2-6400. DDR2 SDRAM is now available at a clock rate of 533 MHz generally described as DDR2-1066 and the corresponding DIMMs are known as PC2-8500 (also named PC2-8600 depending on the manufacturer). Performance up to DDR2-1250 (PC2-10000) is available for a price.
Note that because internal operations are at 1/2 the clock rate, DDR2-400 memory (internal clock rate 100 MHz) has somewhat higher latency than DDR-400 (internal clock rate 200 MHz).
DDR3 SDRAM
DDR3 continues the trend, doubling the minimum read or write unit to 8 consecutive words. This allows another doubling of bandwidth and external bus rate without having to change the clock rate of internal operations, just the width. To maintain 800–1600 M transfers/s (both edges of a 400–800 MHz clock), the internal RAM array has to perform 100–200 M fetches per second.Again, with every doubling, the downside is the increased latency
Latency (engineering)
Latency is a measure of time delay experienced in a system, the precise definition of which depends on the system and the time being measured. Latencies may have different meaning in different contexts.-Packet-switched networks:...
. As with all DDR SDRAM generations, commands are still restricted to one clock edge and command latencies are given in terms of clock cycles, which are half the speed of the usually quoted transfer rate (a CAS latency
CAS Latency
Column Address Strobe latency, or CL, is the delay time between the moment a memory controller tells the memory module to access a particular memory column on a RAM memory module, and the moment the data from given array location is available on the module's output pins...
of 8 with DDR3-800 is 8/(400 MHz) = 20 ns, exactly the same latency of CAS2 on PC100
PC100
PC100 is a standard for internal removable computer random access memory, defined by the JEDEC. PC100 refers to Synchronous DRAM operating at a clock frequency of 100 MHz, on a 64-bit-wide bus, at a voltage of 3.3 V. PC100 is available in 168-pin DIMM and 144-pin SO-DIMM form factors...
SDR SDRAM).
DDR3 memory chips are being made commercially, and computer systems are available that use them as of the second half of 2007, with expected significant usage in 2008. Initial clock rates were 400 and 533 MHz, which are described as DDR3-800 and DDR3-1066 (PC3-6400 and PC3-8500 modules), but 667 and 800 MHz, described as DDR3-1333 and DDR3-1600 (PC3-10600 and PC3-12800 modules) are now common. Performance up to DDR3-2200 (PC3 17600 modules) are available for a price.
DDR4 SDRAM
DDR4 SDRAM will be the successor to DDR3 SDRAMDDR3 SDRAM
In computing, DDR3 SDRAM, an abbreviation for double data rate type three synchronous dynamic random access memory, is a modern kind of dynamic random access memory with a high bandwidth interface. It is one of several variants of DRAM and associated interface techniques used since the early 1970s...
. It was revealed at the Intel Developer Forum
Intel Developer Forum
Intel Developer Forum , is a gathering of technologists to discuss Intel products and products based around Intel products. The first IDF was in 1997...
in San Francisco in 2008, and is due to be released to market during 2011. The timing has varied considerably during its development - it was originally expected to be released in 2012, and later (during 2010) expected to be released in 2015, before samples were announced in early 2011 and manufacturers began to announce that commercial production and release to market was anticipated in 2012. DDR4 is expected to reach mass market adoption around 2015, which is comparable with the approximately 5 years taken for DDR3 to achieve mass market transition over DDR2.
The new chips are expected to run at 1.2 V
Volt
The volt is the SI derived unit for electric potential, electric potential difference, and electromotive force. The volt is named in honor of the Italian physicist Alessandro Volta , who invented the voltaic pile, possibly the first chemical battery.- Definition :A single volt is defined as the...
or less, versus the 1.5 V of DDR3 chips, and have in excess of 2 billion data transfers per second. They are expected to be introduced at frequency rates of 2133 MHz, estimated to rise to a potential 4266 MHz and lowered voltage of 1.05 V by 2013.
In February 2009, Samsung
Samsung
The Samsung Group is a South Korean multinational conglomerate corporation headquartered in Samsung Town, Seoul, South Korea...
validated 40 nm DRAM chips, considered a "significant step" towards DDR4 development since as of 2009, current DRAM chips were only beginning to migrate to a 50 nm process. In January 2011, Samsung
Samsung
The Samsung Group is a South Korean multinational conglomerate corporation headquartered in Samsung Town, Seoul, South Korea...
announced the completion and release for testing of a 30 nm 2 GB DDR4 DRAM module. It has a maximum bandwidth of 2.13 Gbit/s at 1.2 V, uses pseudo open drain technology and draws 40% less power than an equivalent DDR3 module.
Feature map
| Type | Feature changes |
|---|---|
| SDRAM | Signal: LVTTL |
| DDR1 DDR SDRAM Double data rate synchronous dynamic random access memory is a class of memory integrated circuits used in computers. DDR SDRAM has been superseded by DDR2 SDRAM and DDR3 SDRAM, neither of which are either forward or backward compatible with DDR SDRAM, meaning that DDR2 or DDR3 memory modules... |
Access is ≥2 words Double clocked Double data rate In computing, a computer bus operating with double data rate transfers data on both the rising and falling edges of the clock signal. This is also known as double pumped, dual-pumped, and double transition.... per cycle Signal: SSTL 2 Stub Series Terminated Logic Stub Series Terminated Logic is a group of electrical standards for driving transmission lines commonly used with DRAM based DDR memory IC's and memory modules . Primarily designed for driving the DDR SDRAM modules used in computer memory... (2.5V) |
| DDR2 DDR2 SDRAM DDR2 SDRAM is a double data rate synchronous dynamic random-access memory interface. It supersedes the original DDR SDRAM specification and has itself been superseded by DDR3 SDRAM... |
Access is ≥4 words "Burst terminate" removed 4 units used in parallel per cycle Internal operations are at 1/2 the clock rate. Signal: SSTL 18 Stub Series Terminated Logic Stub Series Terminated Logic is a group of electrical standards for driving transmission lines commonly used with DRAM based DDR memory IC's and memory modules . Primarily designed for driving the DDR SDRAM modules used in computer memory... (1.8V) |
| DDR3 DDR3 SDRAM In computing, DDR3 SDRAM, an abbreviation for double data rate type three synchronous dynamic random access memory, is a modern kind of dynamic random access memory with a high bandwidth interface. It is one of several variants of DRAM and associated interface techniques used since the early 1970s... |
Access is ≥8 words Signal: SSTL 15 Stub Series Terminated Logic Stub Series Terminated Logic is a group of electrical standards for driving transmission lines commonly used with DRAM based DDR memory IC's and memory modules . Primarily designed for driving the DDR SDRAM modules used in computer memory... (1.5V) Much longer CAS latencies |
| DDR4 DDR4 SDRAM In computing, DDR4 SDRAM, an abbreviation for double data rate type four synchronous dynamic random-access memory, is a type of dynamic random-access memory with a high bandwidth interface currently under development and expected market release in 2012. As a "next generation" successor to DDR3... |
point-to-point (single module per channel) |
Failed successors
In addition to DDR, there were several other proposed memory technologies to succeed SDR SDRAM.Rambus DRAM (RDRAM)
RDRAMRDRAM
Direct Rambus DRAM or DRDRAM is a type of synchronous dynamic RAM. RDRAM was developed by Rambus inc., in the mid-1990s as a replacement for then-prevalent DIMM SDRAM memory architecture....
was a proprietary technology that competed against DDR. Its relatively high price and disappointing performance (resulting from high latencies and a narrow 16-bit data channel versus DDR's 64 bit channel) caused it to lose the race to succeed SDR DRAM.
Synchronous-Link DRAM (SLDRAM)
SLDRAM boasted higher performance and competed against RDRAM. It was developed during the late 1990s by the SLDRAM Consortium, which consisted of about 20 major computer industry manufacturers. It is an open standardOpen standard
An open standard is a standard that is publicly available and has various rights to use associated with it, and may also have various properties of how it was designed . There is no single definition and interpretations vary with usage....
and does not require licensing fees. The specifications called for a 64-bit bus running at a 200 MHz clock frequency. This is achieved by all signals being on the same line and thereby avoiding the synchronization time of multiple lines. Like DDR SDRAM
DDR SDRAM
Double data rate synchronous dynamic random access memory is a class of memory integrated circuits used in computers. DDR SDRAM has been superseded by DDR2 SDRAM and DDR3 SDRAM, neither of which are either forward or backward compatible with DDR SDRAM, meaning that DDR2 or DDR3 memory modules...
, SLDRAM uses an double-pumped bus, giving it an effective speed of 400 MT/s.
Virtual Channel Memory (VCM) SDRAM
VCM was a proprietary type of SDRAM that was designed by NECNEC
, a Japanese multinational IT company, has its headquarters in Minato, Tokyo, Japan. NEC, part of the Sumitomo Group, provides information technology and network solutions to business enterprises, communications services providers and government....
, but released as an open standard with no licensing fees. VCM creates a state in which the various system processes can be assigned their own virtual channel, thus increasing the overall system efficiency by avoiding the need to have processes share buffer space. This is accomplished by creating different "blocks" of memory, allowing each individual memory block to interface separately with the memory controller and have its own buffer space. VCM has higher performance than SDRAM because it has significantly lower latencies. The technology was a potential competitor of RDRAM
RDRAM
Direct Rambus DRAM or DRDRAM is a type of synchronous dynamic RAM. RDRAM was developed by Rambus inc., in the mid-1990s as a replacement for then-prevalent DIMM SDRAM memory architecture....
because VCM was not nearly as expensive as RDRAM was. A Virtual Channel Memory (VCM) module is mechanically and electrically compatible with standard SDRAM, but must be recognized by the memory controller
Memory controller
The memory controller is a digital circuit which manages the flow of data going to and from the main memory. It can be a separate chip or integrated into another chip, such as on the die of a microprocessor...
. Few motherboards were ever produced with VCM support.
See also
- GDDRGDDRGDDR or Graphic Double Data Rate memory refers to memory specifically designed for use on graphics cards. GDDR is distinct from the more widely known DDR SDRAM types such as DDR3, although they share some technologies - including double data rate design - in common...
(graphics DDR) and its subtypes GDDR2, GDDR3GDDR3Graphics Double Data Rate 3 is a graphics card-specific memory technology, designed by ATI Technologies with the collaboration of JEDEC.It has much the same technological base as DDR2, but the power and heat dispersal requirements have been reduced somewhat, allowing for higher performance memory...
, GDDR4GDDR4GDDR4 SDRAM is a type of graphics card memory specified by the JEDEC Semiconductor Memory Standard. It is a rival medium to Rambus's XDR DRAM...
, and GDDR5GDDR5GDDR5 SDRAM is a type of high performance DRAM graphics card memory designed for computer applications requiring high bandwidth... - SDRAM latencySDRAM latencySDRAM latency refers to delays in transmitting data between the CPU and SDRAM. SDRAM latency is often measured in memory bus clock cycles. However, the CPU operates faster than the memory, so it must wait while the proper segment of memory is located and read, before the data can be sent back...
- List of device bandwidths
- Serial presence detectSerial presence detectSerial presence detect refers to a standardized way to automatically access information about a computer memory module. Earlier 72-pin SIMMs included 5 pins which provided 5 bits of parallel presence detect data, but the 168-pin DIMM standard changed to a serial presence detect to encode much...
- EEPROM with timing data on SDRAM modules - SDRAM Tutorial - Flash website built by Tel-Aviv University students
- A concise but thorough review of SDRAM architecture/terminology and command timing dependencies in High-Performance DRAM System Design Constraints and Considerations, a master thesis from the University of Maryland.