SDRAM latency
Encyclopedia
SDRAM latency refers to delays in transmitting data between the CPU
and SDRAM
. SDRAM latency is often measured in memory bus clock cycles
. However, the CPU operates faster than the memory, so it must wait while the proper segment of memory is located and read, before the data can be sent back. This also adds to the total SDRAM latency.
SDRAM access has four main measurements (quantified in FSB
clock cycles) important in defining the SDRAM latency in a given computer (the 't' prefixes are for 'time'):
tCAS
tRCD (RAS to CAS Delay)
tRP (RAS Precharge)
tRAS (Row Active Time)
Pictorially the timings operate as follows:
Initially, the row address is sent to the DRAM. After tRCD, the row is open and may be accessed. Because this is an SDRAM, multiple column access can be in progress at once. Each read takes time tCAS. When we are done accessing the column, we precharge the SDRAM, which returns us to the starting state after time tRP.
Two other time limits that must also be maintained are tRAS, the time for the refresh of the row to complete before it may be closed again, and tWR, the time that must elapse after the last write before the row may be closed.
(DDR) RAM, where two parts of each clock cycle are used)
Computer users don't need to worry about setting the SDRAM latency because the computer will auto-adjust the RAM timing based on the Serial Presence Detect
(SPD) ROM
inside the RAM packaging that defines the four timing values, decided by the RAM manufacturer. Although the SDRAM latency timing can often be adjusted manually, using lower latency settings than the module's rating (overclocking
) may cause a computer to crash
, due to memory read/write errors, or fail to boot
.
Regardless of the said risk, power users typically perform overclocking because no manufacturer attempts to set the best settings in the SPD ROM due to economies of scale incurring from(among others) fabrication process variations - extra binning require extended testing and validation. Due to the loose settings of manufacturers, an SDRAM with SPD 6-6-6-18 and a command rate of 2T being able to support 5-5-4-14 timings with a command rate of 1T and function without instability, with all other settings being the same. The manufacturer may also only need to sell a specific, slower specification for compatibility purposes and may program higher grade modules with lower clock SPD timings due to being cheaper for them(and/or slower chips not being available anymore). Computer power users edit the bios, or use programs such as Memset, to reduce the default latencies or increase clock to the least that the modules can practically function, although they may then not work well up to the module's temperature rating or may require extra voltage to do so.
Central processing unit
The central processing unit is the portion of a computer system that carries out the instructions of a computer program, to perform the basic arithmetical, logical, and input/output operations of the system. The CPU plays a role somewhat analogous to the brain in the computer. The term has been in...
and SDRAM
SDRAM
Synchronous dynamic random access memory is dynamic random access memory that is synchronized with the system bus. Classic DRAM has an asynchronous interface, which means that it responds as quickly as possible to changes in control inputs...
. SDRAM latency is often measured in memory bus clock cycles
Clock signal
In electronics and especially synchronous digital circuits, a clock signal is a particular type of signal that oscillates between a high and a low state and is utilized like a metronome to coordinate actions of circuits...
. However, the CPU operates faster than the memory, so it must wait while the proper segment of memory is located and read, before the data can be sent back. This also adds to the total SDRAM latency.
SDRAM access
SDRAM is notationally organized into a grid like pattern, with "rows" and "columns". The data stored in SDRAM comes in blocks, defined by the coordinates of the row and column of the specific information. The steps for the memory controller to access data in SDRAM follow in order:- First, the SDRAM is in an idle state.
- The controller issues the "active" command. It activates a certain row, as indicated by the address lines, in the SDRAM chip for accessing. This command typically takes a few clock cycles.
- After the delay, column address and either "read" or "write" command is issued. Typically the read or write command can be repeated every clock cycle for different column addresses (or a burst mode read can be performed). The read data isn't however available until a few clock cycles later, because the memory is pipelined.
- When an access is requested to another row, the current row has to be deactivated by issuing the "precharge" command. The precharge command takes a few clock cycles before a new "active" command can be issued.
SDRAM access has four main measurements (quantified in FSB
Front side bus
A front-side bus is a computer communication interface often used in computers during the 1990s and 2000s.It typically carries data between the central processing unit and a memory controller hub, known as the northbridge....
clock cycles) important in defining the SDRAM latency in a given computer (the 't' prefixes are for 'time'):
tCAS
- The number of clock cycles needed to access a certain column of data in SDRAM. CAS latencyCAS LatencyColumn Address Strobe latency, or CL, is the delay time between the moment a memory controller tells the memory module to access a particular memory column on a RAM memory module, and the moment the data from given array location is available on the module's output pins...
, or simply CAS, is known as Column Address Strobe time, sometimes referred to as tCL.
tRCD (RAS to CAS Delay)
- The number of clock cycles needed between a row address strobe (RAS) and a CAS. It is the time required between the computer defining the row and column of the given memory block and the actual read or write to that location. tRCD stands for Row address to Column address Delay time.
tRP (RAS Precharge)
- The number of clock cycles needed to terminate access to an open row of memory, and open access to the next row. It stands for Row Precharge time.
tRAS (Row Active Time)
- The minimum number of clock cycles needed to access a certain row of data in RAM between the data request and the precharge command. It's known as active to precharge delay. According to Mushkin.com, in practice for DDR SDRAM, this should be set to at least tRCD + tCAS + 2 to allow enough time for data to be streamed out. http://www.mushkin.com/doc/support/papers/latency.asp. It stands for Row Address Strobe time.
Pictorially the timings operate as follows:
| Row access | | Column accesses | | Precharge | |||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| tRCD = 3 | tCAS (R) = 3 | tRP = 3 | |||||||||
| tWR (Write) = 5 | |||||||||||
| tCAS (R) | |||||||||||
| tCAS (R) | |||||||||||
| tRAS = 9 | |||||||||||
Initially, the row address is sent to the DRAM. After tRCD, the row is open and may be accessed. Because this is an SDRAM, multiple column access can be in progress at once. Each read takes time tCAS. When we are done accessing the column, we precharge the SDRAM, which returns us to the starting state after time tRP.
Two other time limits that must also be maintained are tRAS, the time for the refresh of the row to complete before it may be closed again, and tWR, the time that must elapse after the last write before the row may be closed.
Measurements
Lower latency results in better performance, although the difference will not be significant. RAM speeds are given by the four numbers above, commonly in the format "tCAS-tRCD-tRP-tRAS". For example, latency values given as 2.5-3-3-8 would indicate tCAS=2.5, tRCD=3, tRP=3, tRAS=8. (Note that 0.5 values of latency (such as 2.5) are only possible in double data rateDouble data rate
In computing, a computer bus operating with double data rate transfers data on both the rising and falling edges of the clock signal. This is also known as double pumped, dual-pumped, and double transition....
(DDR) RAM, where two parts of each clock cycle are used)
Computer users don't need to worry about setting the SDRAM latency because the computer will auto-adjust the RAM timing based on the Serial Presence Detect
Serial Presence Detect
Serial presence detect refers to a standardized way to automatically access information about a computer memory module. Earlier 72-pin SIMMs included 5 pins which provided 5 bits of parallel presence detect data, but the 168-pin DIMM standard changed to a serial presence detect to encode much...
(SPD) ROM
Read-only memory
Read-only memory is a class of storage medium used in computers and other electronic devices. Data stored in ROM cannot be modified, or can be modified only slowly or with difficulty, so it is mainly used to distribute firmware .In its strictest sense, ROM refers only...
inside the RAM packaging that defines the four timing values, decided by the RAM manufacturer. Although the SDRAM latency timing can often be adjusted manually, using lower latency settings than the module's rating (overclocking
Overclocking
Overclocking is the process of operating a computer component at a higher clock rate than it was designed for or was specified by the manufacturer, but some manufacturers purposely underclock their components to improve battery life. Many people just overclock or 'rightclock' their hardware to...
) may cause a computer to crash
Crash (computing)
A crash in computing is a condition where a computer or a program, either an application or part of the operating system, ceases to function properly, often exiting after encountering errors. Often the offending program may appear to freeze or hang until a crash reporting service documents...
, due to memory read/write errors, or fail to boot
Booting
In computing, booting is a process that begins when a user turns on a computer system and prepares the computer to perform its normal operations. On modern computers, this typically involves loading and starting an operating system. The boot sequence is the initial set of operations that the...
.
Regardless of the said risk, power users typically perform overclocking because no manufacturer attempts to set the best settings in the SPD ROM due to economies of scale incurring from(among others) fabrication process variations - extra binning require extended testing and validation. Due to the loose settings of manufacturers, an SDRAM with SPD 6-6-6-18 and a command rate of 2T being able to support 5-5-4-14 timings with a command rate of 1T and function without instability, with all other settings being the same. The manufacturer may also only need to sell a specific, slower specification for compatibility purposes and may program higher grade modules with lower clock SPD timings due to being cheaper for them(and/or slower chips not being available anymore). Computer power users edit the bios, or use programs such as Memset, to reduce the default latencies or increase clock to the least that the modules can practically function, although they may then not work well up to the module's temperature rating or may require extra voltage to do so.