Mobile DDR is type of double data rate

Double data rate

In computing, a computer bus operating with double data rate transfers data on both the rising and falling edges of the clock signal. This is also known as double pumped, dual-pumped, and double transition....

 synchronous DRAM

SDRAM

Synchronous dynamic random access memory is dynamic random access memory that is synchronized with the system bus. Classic DRAM has an asynchronous interface, which means that it responds as quickly as possible to changes in control inputs...

 for mobile computers.

Original LPDDR

The original low-power DDR (sometimes, in hindsight, called LPDDR1) is a slightly modified form of DDR SDRAM

DDR SDRAM

Double data rate synchronous dynamic random access memory is a class of memory integrated circuits used in computers. DDR SDRAM has been superseded by DDR2 SDRAM and DDR3 SDRAM, neither of which are either forward or backward compatible with DDR SDRAM, meaning that DDR2 or DDR3 memory modules...

, with several changes to reduce overall power consumption.

Most significant, the supply voltage is reduced from 2.5 to 1.8 V. Additional savings come from temperature-compensated refresh (DRAM requires refresh less often at low temperatures), partial array self refresh, and a "deep power down" mode which sacrifices all memory contents. Additionally, chips are smaller, using less board space than their non-mobile equivalents. Samsung

Samsung

The Samsung Group is a South Korean multinational conglomerate corporation headquartered in Samsung Town, Seoul, South Korea...

 and Micron

Micron Technology

Micron Technology, Inc. is an American multinational corporation based in Boise, Idaho, USA, best known for producing many forms of semiconductor devices. This includes DRAM, SDRAM, flash memory, SSD and CMOS image sensing chips. Consumers may be more familiar with its consumer brand Crucial...

 are two of the main providers of this technology, and is used in tablet computing devices such as the Apple

Apple

The apple is the pomaceous fruit of the apple tree, species Malus domestica in the rose family . It is one of the most widely cultivated tree fruits, and the most widely known of the many members of genus Malus that are used by humans. Apple grow on small, deciduous trees that blossom in the spring...

 iPad

IPad

The iPad is a line of tablet computers designed, developed and marketed by Apple Inc., primarily as a platform for audio-visual media including books, periodicals, movies, music, games, and web content. The iPad was introduced on January 27, 2010 by Apple's then-CEO Steve Jobs. Its size and...

, Samsung Galaxy Tab

Samsung Galaxy Tab

The Samsung Galaxy Tab is an Android-based tablet computer produced by Samsung introduced on 2 September 2010 at the IFA in Berlin.The Galaxy Tab has a TFT-LCD touchscreen, Wi-Fi capability, a 1.0 GHz ARM Cortex-A8 Samsung Exynos 3110 processor, the Swype input system, a 3.2 MP rear-facing...

 and Motorola Droid X

Motorola Droid X

The Motorola Droid X is a smartphone manufactured by Motorola Mobility, Inc. that runs the Android 2.3 software; the version of the hardware released in Mexico is called the Motorola Motoroi X. The Droid X has been distributed since July, 2010 by Verizon Wireless in the United States and Iusacell...

.

LPDDR2

A new JEDEC

JEDEC

The JEDEC Solid State Technology Association, formerly known as the Joint Electron Devices Engineering Council , is an independent semiconductor engineering trade organization and standardization body...

 standard JESD209-2E defines a more dramatically revised low-power DDR interface. It is not compatible with either DDR1 or DDR2 SDRAM

DDR2 SDRAM

DDR2 SDRAM is a double data rate synchronous dynamic random-access memory interface. It supersedes the original DDR SDRAM specification and has itself been superseded by DDR3 SDRAM...

, but can accommodate either:

• LPDDR2-S2: 2n prefetch memory (like DDR1),
• LPDDR2-S4: 4n prefetch memory (like DDR2), or
• LPDDR2-N: Non-volatile (NAND flash) memory.

Low-power states are similar to basic LPDDR, with some additional partial array refresh options.

Timing parameters are specified for LPDDR-200 to LPDDR-1066 (clock frequencies of 100 to 533 MHz).

Working at 1.2 V, LPDDR2 multiplexes the control and address lines onto a 10-bit double data rate

Double data rate

In computing, a computer bus operating with double data rate transfers data on both the rising and falling edges of the clock signal. This is also known as double pumped, dual-pumped, and double transition....

 CA bus. The commands are similar to those of normal SDRAM, except for the reassignment of the precharge and burst terminate opcodes:

LPDDR2 command encoding

CK	CA0	CA1	CA2	CA3	CA4	CA5	CA6	CA7	CA8	CA9	Operation
↑	H	H	H	—							NOP
↓	—
↑	H	H	L	H	H	—					Precharge all banks
↓	—
↑	H	H	L	H	L	—		BA2	BA1	BA0	Precharge one bank
↓	—
↑	H	H	L	H	A30	A31	A32	BA2	BA1	BA0	Preactive (LPDDR2-N only)
↓	A20	A21	A22	A23	A24	A25	A26	A27	A28	A29
↑	H	H	L	L	—						Burst terminate
↓	—
↑	H	L	H	reserved		C1	C2	BA2	BA1	BA0	Read (AP=auto-precharge)
↓	AP	C3	C4	C5	C6	C7	C8	C9	C10	C11
↑	H	L	L	reserved		C1	C2	BA2	BA1	BA0	Write (AP=auto-precharge)
↓	AP	C3	C4	C5	C6	C7	C8	C9	C10	C11
↑	L	H	R8	R9	R10	R11	R12	BA2	BA1	BA0	Activate (R0–14=Row address)
↓	R0	R1	R2	R3	R4	R5	R6	R7	R13	R14
↑	L	H	A15	A16	A17	A18	A19	BA2	BA1	BA0	Activate (LPDDR2-N only)
↓	A5	A6	A7	A8	A9	A10	A11	A12	A13	A14
↑	L	L	H	H	—						Refresh all banks (LPDDR2-Sx only)
↓	—
↑	L	L	H	L	—						Refresh one bank (Round-robin addressing)
↓	—
↑	L	L	L	H	MA0	MA1	MA2	MA3	MA4	MA5	Mode register read (MA0–7=Address)
↓	MA6	MA7	—
↑	L	L	L	L	MA0	MA1	MA2	MA3	MA4	MA5	Mode register write (OP0–7=Data)
↓	MA6	MA7	OP0	OP1	OP2	OP3	OP4	OP5	OP6	OP7

Column address bit C0 is never transferred, and is assumed to be zero. Burst transfers thus always begin at even addresses.

LPDDR2 also has an active-low chip select (when high, everything is a NOP) and clock enable CKE signal, which operate like SDRAM. Also like SDRAM, the command sent on the cycle that CKE is first dropped selects the power-down state:

• If the chip is active, it freezes in place.
• If the command is a NOP ( low or CA0–2 = HHH), the chip idles.
• If the command is a refresh command (CA0–2 = LLH), the chip enters the self-refresh state.
• If the command is a burst terminate (CA0–2 = HHL), the chip enters the deep power-down state. (A full reset sequence is required when leaving.)

The mode registers have been greatly expanded compared to conventional SDRAM, with an 8-bit address space, and the ability to read them back. Although smaller than a serial presence detect

Serial presence detect

Serial presence detect refers to a standardized way to automatically access information about a computer memory module. Earlier 72-pin SIMMs included 5 pins which provided 5 bits of parallel presence detect data, but the 168-pin DIMM standard changed to a serial presence detect to encode much...

EEPROM, enough information is included to obviate the need for one.

S2 devices smaller than 4 Gbit, and S4 devices smaller than 1 Gbit have only 4 banks. They ignore the BA2 signal, and do not support per-bank refresh.

Non-volatile memory devices do not use the refresh commands, and reassign the precharge command to transfer address bits A20 and up. The low-order bits (A19 and down) are transferred by a following Activate command. This transfers the selected row from the memory array to one of 4 or 8 (selected by the BA bits) row data buffers, where they can be read by a Read command. Unlike DRAM, the bank address bits are not part of the memory address; any address can be transferred to any row data buffer. A row data buffer may be from 32 to 4096 bytes long, depending on the type of memory. Rows larger than 32 bytes ignore some of the low-order address bits in the Activate command. Rows smaller than 4096 bytes ignore some of the high-order address bits in the Read command.

Non-volatile memory does not support the Write command to row data buffers. Rather, a series of control registers in a special address region support Read and Write commands, which can be used to erase and program the memory array.

External links

• Micron
• Elpida
• Nanya