Delay calculation
Encyclopedia
Delay calculation is the term used in integrated circuit design
for the calculation of the gate delay of a single logic gate
and the wires attached to it. By contrast, static timing analysis
computes the delays of entire paths, using delay calculation to determine the delay of each gate and wire.
There are many methods used for delay calculation for the gate itself. The choice depends primarily on the speed and accuracy required:
Similarly there are many ways to calculate the delay of a wire. The delay of a wire will normally be different to each destination. In order of increasing accuracy (and decreasing speed), the most common methods are:
Often, it makes sense to combine the calculation of a gate and all the wire connected to its output. This combination is often called the stage delay.
The delay of a wire or gate may also depend on the behaviour of the nearby components. This is one of the main effects that is analyzed during signal integrity
checks.
In this context, the blocks are logic gate
s such as NAND, OR, AND, etc. Although in reality these gates will be composed of transistors, a semi-custom engineer will only be aware of the delay information from input pin to output pin, called a timing arc. The 2D table represents information about the variability of the gate's delay with respect to the two independent variables, usually the rate of change of the signal at the input and the load at the output pin. These two variable are called slew and load in design parlance.
A static timing analysis
engine will first calculate the delay of the individual cells and string them together to do further analysis.
Integrated circuit design
Integrated circuit design, or IC design, is a subset of electrical engineering and computer engineering, encompassing the particular logic and circuit design techniques required to design integrated circuits, or ICs...
for the calculation of the gate delay of a single logic gate
Logic gate
A logic gate is an idealized or physical device implementing a Boolean function, that is, it performs a logical operation on one or more logic inputs and produces a single logic output. Depending on the context, the term may refer to an ideal logic gate, one that has for instance zero rise time and...
and the wires attached to it. By contrast, static timing analysis
Static timing analysis
Static Timing Analysis is a method of computing the expected timing of a digital circuit without requiring simulation.High-performance integrated circuits have traditionally been characterized by the clock frequency at which they operate...
computes the delays of entire paths, using delay calculation to determine the delay of each gate and wire.
There are many methods used for delay calculation for the gate itself. The choice depends primarily on the speed and accuracy required:
- Circuit simulators such as SPICESPICESPICE is a general-purpose, open source analog electronic circuit simulator.It is a powerful program that is used in integrated circuit and board-level design to check the integrity of circuit designs and to predict circuit behavior.- Introduction :Unlike board-level designs composed of discrete...
may be used. This is the most accurate, but slowest, method. - Two dimensional tables are commonly used in applications such as logic synthesisLogic synthesisIn electronics, logic synthesis is a process by which an abstract form of desired circuit behavior, typically register transfer level , is turned into a design implementation in terms of logic gates. Common examples of this process include synthesis of HDLs, including VHDL and Verilog...
, placementPlacement (EDA)Placement is an essential step in electronic design automation - the portion of the physical design flow that assigns exact locations for various circuitcomponents within the chip’s core area...
and routingRouting (EDA)In electronic design, wire routing, commonly called simply routing, is a step in the design of printed circuit boards and integrated circuits . It builds on a preceding step, called placement, which determines the location of each active element of an IC or component on a PCB...
. These tables take an output load and input slope, and generate a circuit delay and output slope. - A very simple model called the K-factor model is sometimes used. This approximates the delay as a constant plus k times the load capacitance.
- A more complex model called Delay Calculation Language, or DCL, calls a user-defined program whenever a delay value is required. This allows arbitrarily complex models to be represented, but raises significant software engineering issues.
- Logical effortLogical effortThe method of logical effort, a term coined by Ivan Sutherland and Bob Sproull in 1991, is a straightforward technique used to estimate delay in a CMOS circuit...
provides a simple delay calculation that accounts for gate sizing and is analytically tractable.
Similarly there are many ways to calculate the delay of a wire. The delay of a wire will normally be different to each destination. In order of increasing accuracy (and decreasing speed), the most common methods are:
- Lumped C. The entire wire capacitance is applied to the gate output, and the delay through the wire itself is ignored.
- Elmore delayElmore delayElmore delay is a simple approximation to the delay through an RC network in an electronic system. It is often used in applications such as logic synthesis, delay calculation, static timing analysis, placement and routing, since it is simple to compute and is reasonably accurate...
is a simple approximation, often used where speed of calculation is important but the delay through the wire itself cannot be ignored. It uses the R and C values of the wire segments in a simple calculation. The delay of each wire segment is the R of that segment times the downstream C. Then all delays are summed from the root. (This assumes the network is tree structured, true of most nets in chips. In this case the Elmore delay can be calculated in time O(N) with two tree traversals. If the network is not tree structured the Elmore delay can still be computed, but involves matrix calculations.) - Moment matching is a more sophisticated analytical method. It can be thought of as either matching multiple moments in the time domain, or finding a good rational approximation (a Padé approximationPadé approximantPadé approximant is the "best" approximation of a function by a rational function of given order - under this technique, the approximant's power series agrees with the power series of the function it is approximating....
) in the frequency domain. (These are very closely related - see Laplace transform.) It can also be thought of a generalization of Elmore delay, which matches the first moment in the time domain (or computes a one-pole approximation in the frequency domain - they are equivalent). The first use of this technique, AWE, used explicit moment matching. Newer methods such as PRIMA and PVL use implicit moment matching, based on Krylov subspaceKrylov subspaceIn linear algebra, the order-r Krylov subspace generated by an n-by-n matrix A and a vector b of dimension n is the linear subspace spanned by the images of b under the first r powers of A , that is,...
s. These methods are slower than Elmore but more accurate. Compared to circuit simulation they are faster but less accurate. - Circuit simulators such as SPICESPICESPICE is a general-purpose, open source analog electronic circuit simulator.It is a powerful program that is used in integrated circuit and board-level design to check the integrity of circuit designs and to predict circuit behavior.- Introduction :Unlike board-level designs composed of discrete...
may be used. This is usually the most accurate, but slowest, method. - DCL, as defined above, can be used for interconnect as well as gate delay.
Often, it makes sense to combine the calculation of a gate and all the wire connected to its output. This combination is often called the stage delay.
The delay of a wire or gate may also depend on the behaviour of the nearby components. This is one of the main effects that is analyzed during signal integrity
Signal integrity
Signal integrity or SI is a set of measures of the quality of an electrical signal. In digital electronics, a stream of binary values is represented by a voltage waveform. However, digital signals are fundamentally analog in nature, and all signals are subject to effects such as noise,...
checks.
Delay Calculation in digital design
In the context of semi-custom digital design, pre-characterized digital information is often abstracted in the form of the above mentioned 2-D look up table (LUT). The idea behind semi-custom design method is to use blocks of pre-built and tested components to build something larger, say, a chip.In this context, the blocks are logic gate
Logic gate
A logic gate is an idealized or physical device implementing a Boolean function, that is, it performs a logical operation on one or more logic inputs and produces a single logic output. Depending on the context, the term may refer to an ideal logic gate, one that has for instance zero rise time and...
s such as NAND, OR, AND, etc. Although in reality these gates will be composed of transistors, a semi-custom engineer will only be aware of the delay information from input pin to output pin, called a timing arc. The 2D table represents information about the variability of the gate's delay with respect to the two independent variables, usually the rate of change of the signal at the input and the load at the output pin. These two variable are called slew and load in design parlance.
A static timing analysis
Static timing analysis
Static Timing Analysis is a method of computing the expected timing of a digital circuit without requiring simulation.High-performance integrated circuits have traditionally been characterized by the clock frequency at which they operate...
engine will first calculate the delay of the individual cells and string them together to do further analysis.
Statistical delay calculation
As chip dimensions get smaller, the delays of both gates and wires may need to be treated as statistical estimates instead of deterministic quantities. For gates, this requires extensions to the library formats. For wires, this requires methods that can calculate the means and distributions of wire delays. In both cases it is critical to capture the dependence on the underlying variables such a threshold voltage and metal thickness, since these result in correlations among the delays of nearby components. See for an early example.See also
- Electronic design automationElectronic design automationElectronic design automation is a category of software tools for designing electronic systems such as printed circuit boards and integrated circuits...
- Integrated circuit designIntegrated circuit designIntegrated circuit design, or IC design, is a subset of electrical engineering and computer engineering, encompassing the particular logic and circuit design techniques required to design integrated circuits, or ICs...
- Static timing analysisStatic timing analysisStatic Timing Analysis is a method of computing the expected timing of a digital circuit without requiring simulation.High-performance integrated circuits have traditionally been characterized by the clock frequency at which they operate...
- Statistical static timing analysisStatistical static timing analysisConventional static timing analysis has been a stock analysis algorithm for the design of digital circuits over the last 30 years. However, in recent years the increased variation in semiconductor devices and interconnect has introduced a number of issues that cannot be handled by traditional STA...
- Standard Parasitic Exchange FormatStandard Parasitic Exchange FormatStandard Parasitic Exchange Format is an IEEE standard for representing parasitic data of wires in a chip in ASCII format. Resistance, capacitance and inductance of wires in a chip are known as parasitic data...