Standard Parasitic Exchange Format
Encyclopedia
Standard Parasitic Exchange Format (SPEF) is an IEEE standard for representing parasitic data of wires in a chip in ASCII
format. Resistance
, capacitance
and inductance
of wires in a chip are known as parasitic data. SPEF is used for delay calculation
and ensuring signal integrity
of a chip which eventually determines its speed of operation.
SPEF is most popular specification for parasitic exchange between different tools of EDA
domain during any phase of design.
The specification for SPEF is a part of standard 1481-1999 IEEE Standard for Integrated Circuit (IC) Delay and Power Calculation System.
SPEF syntax is roughly:
And repeat (include *END) for other nets.
In order to reduce file size, aliasing is possible, using a name-map:
These symbols (including the *) can then be substituted for the longer words anywhere.
Note: SPEF is not the same as SPF (including DSPF and RSPF). Detailed Standard Parasitic Format is a very different format, meant to be useful in a SPICE
simulation. For example, NET sections do not have endings, and comments should start with two asterisks.
A brief syntax of the DSPF format is as shown:
ASCII
The American Standard Code for Information Interchange is a character-encoding scheme based on the ordering of the English alphabet. ASCII codes represent text in computers, communications equipment, and other devices that use text...
format. Resistance
Electrical resistance
The electrical resistance of an electrical element is the opposition to the passage of an electric current through that element; the inverse quantity is electrical conductance, the ease at which an electric current passes. Electrical resistance shares some conceptual parallels with the mechanical...
, capacitance
Capacitance
In electromagnetism and electronics, capacitance is the ability of a capacitor to store energy in an electric field. Capacitance is also a measure of the amount of electric potential energy stored for a given electric potential. A common form of energy storage device is a parallel-plate capacitor...
and inductance
Inductance
In electromagnetism and electronics, inductance is the ability of an inductor to store energy in a magnetic field. Inductors generate an opposing voltage proportional to the rate of change in current in a circuit...
of wires in a chip are known as parasitic data. SPEF is used for delay calculation
Delay calculation
Delay calculation is the term used in integrated circuit design for the calculation of the gate delay of a single logic gate and the wires attached to it. By contrast, static timing analysis computes the delays of entire paths, using delay calculation to determine the delay of each gate and...
and ensuring signal integrity
Signal integrity
Signal integrity or SI is a set of measures of the quality of an electrical signal. In digital electronics, a stream of binary values is represented by a voltage waveform. However, digital signals are fundamentally analog in nature, and all signals are subject to effects such as noise,...
of a chip which eventually determines its speed of operation.
SPEF is most popular specification for parasitic exchange between different tools of EDA
Electronic design automation
Electronic design automation is a category of software tools for designing electronic systems such as printed circuit boards and integrated circuits...
domain during any phase of design.
The specification for SPEF is a part of standard 1481-1999 IEEE Standard for Integrated Circuit (IC) Delay and Power Calculation System.
SPEF syntax is roughly:
And repeat (include *END) for other nets.
In order to reduce file size, aliasing is possible, using a name-map:
These symbols (including the *) can then be substituted for the longer words anywhere.
Note: SPEF is not the same as SPF (including DSPF and RSPF). Detailed Standard Parasitic Format is a very different format, meant to be useful in a SPICE
SPICE
SPICE is a general-purpose, open source analog electronic circuit simulator.It is a powerful program that is used in integrated circuit and board-level design to check the integrity of circuit designs and to predict circuit behavior.- Introduction :Unlike board-level designs composed of discrete...
simulation. For example, NET sections do not have endings, and comments should start with two asterisks.
A brief syntax of the DSPF format is as shown: