UltraSPARC T3
Encyclopedia
The SPARC T3 microprocessor
(previously known as UltraSPARC T3, codenamed Rainbow Falls, and also known as UltraSPARC KT or Niagara-3 during development) is a multithreading
, multi-core
CPU
produced by Oracle Corporation
(previously Sun Microsystems
). Officially launched on 20 September 2010, it is a member of the SPARC
family, and the successor to the UltraSPARC T2
.
The throughput (SPEC CINT2006 rate) increased in single a socket T3-1 platform in comparison to its predecessor T2+ processor in a dual-socket T5240 platform.
Under simulated web serving workloads, dual-socket based SPARC T3 systems benchmarked better performance than quad-socket(previous generation) UltraSPARC T2+ systems (as well as competing dual and quad socket contemporary systems.)
incorrectly reported in June 2008 that the microprocessor would have 16 cores, each with 16 threads. In September 2009 they published a roadmap that instead showed 8 threads per core. During the Hot Chips 21 conference Sun revealed the chip has a total of 16 cores and 128 threads. According to the ISSCC
2010 presentation:
Support for the UltraSPARC T3 was confirmed on July 16th 2010 when the ARCBot under Twitter noted unpublished PSARC/2010/274 which revealed a new "-xtarget value for UltraSPARC T3" being included in OpenSolaris
.
During Oracle OpenWorld
in San Francisco on September 20, 2010, the processor was officially launched as the "SPARC T3" (dropping the "Ultra" prefix in its name), accompanied by new systems and new reported benchmarks claiming world-record performance. Varied real-world application benchmarks were released with full system disclosures. Internationally recognized SPEC benchmarks were also released with full system disclosures.
Oracle disclosed that SPARC T3 was built with a 40 nm process.
server lines, reducing the total number of servers respectively to four. The new server line includes:
Microprocessor
A microprocessor incorporates the functions of a computer's central processing unit on a single integrated circuit, or at most a few integrated circuits. It is a multipurpose, programmable device that accepts digital data as input, processes it according to instructions stored in its memory, and...
(previously known as UltraSPARC T3, codenamed Rainbow Falls, and also known as UltraSPARC KT or Niagara-3 during development) is a multithreading
Multithreading (computer hardware)
Multithreading computers have hardware support to efficiently execute multiple threads. These are distinguished from multiprocessing systems in that the threads have to share the resources of a single core: the computing units, the CPU caches and the translation lookaside buffer...
, multi-core
Multi-core (computing)
A multi-core processor is a single computing component with two or more independent actual processors , which are the units that read and execute program instructions...
CPU
Central processing unit
The central processing unit is the portion of a computer system that carries out the instructions of a computer program, to perform the basic arithmetical, logical, and input/output operations of the system. The CPU plays a role somewhat analogous to the brain in the computer. The term has been in...
produced by Oracle Corporation
Oracle Corporation
Oracle Corporation is an American multinational computer technology corporation that specializes in developing and marketing hardware systems and enterprise software products – particularly database management systems...
(previously Sun Microsystems
Sun Microsystems
Sun Microsystems, Inc. was a company that sold :computers, computer components, :computer software, and :information technology services. Sun was founded on February 24, 1982...
). Officially launched on 20 September 2010, it is a member of the SPARC
SPARC
SPARC is a RISC instruction set architecture developed by Sun Microsystems and introduced in mid-1987....
family, and the successor to the UltraSPARC T2
UltraSPARC T2
Sun Microsystems' UltraSPARC T2 microprocessor is a multithreading, multi-core CPU. It is a member of the SPARC family, and the successor to the UltraSPARC T1. The chip is sometimes referred to by its codename, Niagara 2...
.
Performance
Overall single socket and multi-socket throughput increased with the T3 processor in systems, providing superior throughput with half the CPU socket requirements to its predecessor.The throughput (SPEC CINT2006 rate) increased in single a socket T3-1 platform in comparison to its predecessor T2+ processor in a dual-socket T5240 platform.
Under simulated web serving workloads, dual-socket based SPARC T3 systems benchmarked better performance than quad-socket(previous generation) UltraSPARC T2+ systems (as well as competing dual and quad socket contemporary systems.)
History
Online IT publication The RegisterThe Register
The Register is a British technology news and opinion website. It was founded by John Lettice, Mike Magee and Ross Alderson in 1994 as a newsletter called "Chip Connection", initially as an email service...
incorrectly reported in June 2008 that the microprocessor would have 16 cores, each with 16 threads. In September 2009 they published a roadmap that instead showed 8 threads per core. During the Hot Chips 21 conference Sun revealed the chip has a total of 16 cores and 128 threads. According to the ISSCC
International Solid-State Circuits Conference
International Solid-State Circuits Conference is a global forum for presentation of advances in solid-state circuits and Systems-on-a-Chip. The Conference offers a unique opportunity for engineers working at the cutting edge of IC design to maintain technical currency, and to network with leading...
2010 presentation:
"A 16-core SPARC SoC processor enables up to 512 threads in a 4-way glueless system to
maximize throughput. The 6MB L2 cache of 461GB/s and the 308-pin SerDes I/O of 2.4Tb/s
support the required bandwidth. Six clock and four voltage domains, as well as power
management and circuit techniques, optimize performance, power, variability and yield trade-offs
across the 377mm2 die."
Support for the UltraSPARC T3 was confirmed on July 16th 2010 when the ARCBot under Twitter noted unpublished PSARC/2010/274 which revealed a new "-xtarget value for UltraSPARC T3" being included in OpenSolaris
OpenSolaris
OpenSolaris was an open source computer operating system based on Solaris created by Sun Microsystems. It was also the name of the project initiated by Sun to build a developer and user community around the software...
.
During Oracle OpenWorld
Oracle OpenWorld
Oracle OpenWorld is an annual Oracle event for business decision-makers, IT management, and line-of-business end users. It is held in San Francisco, California; São Paulo, Brazil; and Shanghai, China. The world's largest conference for Oracle customers and technologists, Oracle OpenWorld San...
in San Francisco on September 20, 2010, the processor was officially launched as the "SPARC T3" (dropping the "Ultra" prefix in its name), accompanied by new systems and new reported benchmarks claiming world-record performance. Varied real-world application benchmarks were released with full system disclosures. Internationally recognized SPEC benchmarks were also released with full system disclosures.
Oracle disclosed that SPARC T3 was built with a 40 nm process.
Features
- 8 or 16 CPU cores
- 8 hardware threadsMultithreading (computer hardware)Multithreading computers have hardware support to efficiently execute multiple threads. These are distinguished from multiprocessing systems in that the threads have to share the resources of a single core: the computing units, the CPU caches and the translation lookaside buffer...
per core - 6 MB Level 2 cacheCPU cacheA CPU cache is a cache used by the central processing unit of a computer to reduce the average time to access memory. The cache is a smaller, faster memory which stores copies of the data from the most frequently used main memory locations...
- 2 embedded coherency controllers
- 6 coherenceCache coherenceIn computing, cache coherence refers to the consistency of data stored in local caches of a shared resource.When clients in a system maintain caches of a common memory resource, problems may arise with inconsistent data. This is particularly true of CPUs in a multiprocessing system...
links - 14 unidirectional lanes per coherence link
- SMPSymmetric multiprocessingIn computing, symmetric multiprocessing involves a multiprocessor computer hardware architecture where two or more identical processors are connected to a single shared main memory and are controlled by a single OS instance. Most common multiprocessor systems today use an SMP architecture...
to 4 sockets without glue circuitry - 4 DDR3 SDRAMDDR3 SDRAMIn computing, DDR3 SDRAM, an abbreviation for double data rate type three synchronous dynamic random access memory, is a modern kind of dynamic random access memory with a high bandwidth interface. It is one of several variants of DRAM and associated interface techniques used since the early 1970s...
memory channels - Embedded PCI ExpressPCI ExpressPCI Express , officially abbreviated as PCIe, is a computer expansion card standard designed to replace the older PCI, PCI-X, and AGP bus standards...
I/O interfaces - 16 Embedded Crypto Acceleration Engines
- 2 Embedded 1GigE/10GigE interfaces
- 2.4Tb/s aggregate throughput per socket
Systems
Oracle's release of their T3 server line refreshed fewer physical products from the former T2 and T2+UltraSPARC T2
Sun Microsystems' UltraSPARC T2 microprocessor is a multithreading, multi-core CPU. It is a member of the SPARC family, and the successor to the UltraSPARC T1. The chip is sometimes referred to by its codename, Niagara 2...
server lines, reducing the total number of servers respectively to four. The new server line includes:
- One Socket SPARC T3-1 2U Rack Server
- One Socket SPARC T3-1B Blade Server
- Two Socket SPARC T3-2 Server
- Four Socket SPARC T3-4 Server
Virtualization
Like the prior T1, T2, and T2+ processors, the T3 supports Hyper-Privileged execution mode. The T3 supports up to 128 Oracle VM Server for SPARC domains (a feature formerly known as Logical Domains).Performance improvement versus T2 and T2+
The SPARC T3 processor is effectively two T2+ processors on a single die. The T3 has:- Double the cores (16) of a T2 or T2+
- Double the 10Gig Ethernet ports (2) over a T2+
- Double the crypto accelerator cores (16) over a T2 or T2+
- Crypto engines support more algorithms than the T2 or T2+ including: DES, 3DES, AES, RC4, SHA1, SHA256/384/512, Kasumi, Galois Field, MD5, RSA to 2048 key, ECC, CRC32
- Over 1.9x Cryptography Performance Throughput Increase
- Faster DDR3 RAM interface over the T2 or T2+ DDR2 interface
- Double the throughput
- Double the memory capacity
- Quadruple the I/O throughput
- Two PCIe 2.0 eight lane interfaces vs one PCIe former generation eight lane interface
See also
- UltraSPARC T1UltraSPARC T1|right|262px|UltraSPARC T1 processorSun Microsystems' UltraSPARC T1 microprocessor, known until its 14 November 2005 announcement by its development codename "Niagara", is a multithreading, multicore CPU...
– The predecessor to T2, also Sun's first multicore and multithread CPU - SPARC T4SPARC T4The SPARC T4 is a SPARC multicore microprocessor introduced in 2011 by Oracle Corporation. The processor is designed to offer high multithreaded performance , as well as high performance single threaded performance from the same chip...