HyperTransport
Encyclopedia
HyperTransport formerly known as Lightning Data Transport (LDT), is a technology for interconnection of computer processors. It is a bidirectional serial/parallel high-bandwidth, low-latency point-to-point link that was introduced on April 2, 2001. The HyperTransport Consortium
HyperTransport Consortium
The HyperTransport Consortium is an industry consortium responsible for specifying and promoting the computer bus technology called HyperTransport. -Organizational Form:...

 is in charge of promoting and developing HyperTransport technology.

Links and rates

HyperTransport comes in four versions—1.x, 2.0, 3.0, and 3.1—which run from 200 MHz
Hertz
The hertz is the SI unit of frequency defined as the number of cycles per second of a periodic phenomenon. One of its most common uses is the description of the sine wave, particularly those used in radio and audio applications....

 to 3.2 GHz
Hertz
The hertz is the SI unit of frequency defined as the number of cycles per second of a periodic phenomenon. One of its most common uses is the description of the sine wave, particularly those used in radio and audio applications....

. It is also a DDR or "Double Data Rate
Double data rate
In computing, a computer bus operating with double data rate transfers data on both the rising and falling edges of the clock signal. This is also known as double pumped, dual-pumped, and double transition....

" connection, meaning it sends data on both the rising and falling edges of the clock signal
Clock signal
In electronics and especially synchronous digital circuits, a clock signal is a particular type of signal that oscillates between a high and a low state and is utilized like a metronome to coordinate actions of circuits...

. This allows for a maximum data rate of 6400 MT
Megatransfer
In computer technology, transfers per second and its more common derivatives gigatransfers per second and megatransfers per second are informal language that refer to the number of operations transferring data that occur in each second in some given data-transfer channel. It is also known as...

/s when running at 3.2 GHz. The operating frequency is auto-negotiated with the motherboard chipset(North Bridge) in current computing. Make sure to check the motherboard specifications to determine the operating frequency before calculating anything.

HyperTransport supports an auto-negotiated bit width, ranging from 2 to 32-bit per link; there are two unidirectional links per HT bus. With HT version 3.1, using full 32-bit links and utilizing the full 3.1 specification's operating frequency, the theoretical transfer rate is 25.6 GB
Gigabyte
The gigabyte is a multiple of the unit byte for digital information storage. The prefix giga means 109 in the International System of Units , therefore 1 gigabyte is...

/s (3.2 GHz × 2 bits/Hz × 32 bits/link ÷ 8 (bits per Byte)) per direction, or 51.2 GB/s aggregated throughput, making it faster than any existing bus standard for PC workstations and servers (such as Intel sponsored PCI Express) as well as making it faster than most bus standards for high-performance computing and networking.

Links of various widths can be mixed together in a single system (for example, one 16-bit link to another CPU and one 8-bit link to a peripheral device), which allows for a wider interconnect between CPUs
Central processing unit
The central processing unit is the portion of a computer system that carries out the instructions of a computer program, to perform the basic arithmetical, logical, and input/output operations of the system. The CPU plays a role somewhat analogous to the brain in the computer. The term has been in...

, and a lower bandwidth interconnect to peripheral
Peripheral
A peripheral is a device attached to a host computer, but not part of it, and is more or less dependent on the host. It expands the host's capabilities, but does not form part of the core computer architecture....

s as appropriate. It also supports link splitting, where a single 16-bit link can be divided into two 8-bit links. The technology also typically has lower latency than other solutions due to its lower overhead.

Electrically, HyperTransport is similar to Low Voltage Differential Signaling
Low voltage differential signaling
Low-voltage differential signaling, or LVDS, is an electrical digital signaling system that can run at very high speeds over inexpensive twisted-pair copper cables. It was introduced in 1994, and has since become very popular in computers, where it forms part of very high-speed networks and...

 (LVDS) operating at 1.2 V. HyperTransport 2.0 added post-cursor transmitter deemphasis
Deemphasis
In telecommunication, de-emphasis is the complement of pre-emphasis, in the antinoise system called emphasis. Emphasis is a system process designed to decrease, , the magnitude of some frequencies with respect to the magnitude of other frequencies in order to improve the overall signal-to-noise...

. HyperTransport 3.0 added scrambling and receiver phase alignment as well as optional transmitter pre-cursor deemphasis.

Packet-oriented

HyperTransport is packet-based, where each packet consists of a set of 32-bit
32-bit
The range of integer values that can be stored in 32 bits is 0 through 4,294,967,295. Hence, a processor with 32-bit memory addresses can directly access 4 GB of byte-addressable memory....

 words, regardless of the physical width of the link. The first word in a packet always contains a command field. Many packets contain a 40-bit address. An additional 32-bit control packet is prepended when 64-bit addressing is required. The data payload is sent after the control packet. Transfers are always padded to a multiple of 32 bits, regardless of their actual length.

HyperTransport packets enter the interconnect in segments known as bit times. The number of bit times required depends on the link width. HyperTransport also supports system management messaging, signaling interrupts, issuing probes to adjacent devices or processors, I/O
I/O
I/O may refer to:* Input/output, a system of communication for information processing systems* Input-output model, an economic model of flow prediction between sectors...

 transactions, and general data transactions. There are two kinds of write commands supported: posted and non-posted. Posted writes do not require a response from the target. This is usually used for high bandwidth devices such as Uniform Memory Access
Uniform Memory Access
Uniform Memory Access is a shared memory architecture used in parallel computers.All the processors in the UMA model share the physical memory uniformly...

 traffic or Direct memory access
Direct memory access
Direct memory access is a feature of modern computers that allows certain hardware subsystems within the computer to access system memory independently of the central processing unit ....

 transfers. Non-posted writes require a response from the receiver in the form of a "target done" response. Reads also require a response, containing the read data. HyperTransport supports the PCI consumer/producer ordering model.

Power-managed

HyperTransport also facilitates power management
Power management
Power management is a feature of some electrical appliances, especially copiers, computers and computer peripherals such as monitors and printers, that turns off the power or switches the system to a low-power state when inactive. In computing this is known as PC power management and is built...

 as it is compliant with the Advanced Configuration and Power Interface
Advanced Configuration and Power Interface
In computing, the Advanced Configuration and Power Interface specification provides an open standard for device configuration and power management by the operating system....

 specification. This means that changes in processor sleep states (C states) can signal changes in device states (D states), e.g. powering off disks when the CPU goes to sleep. HyperTransport 3.0 added further capabilities to allow a centralized power management controller to implement power management policies.

Front-side bus replacement

The primary use for HyperTransport is to replace the front-side bus, which is currently different for every type of machine. For instance, a Pentium
Pentium compatible processor
A Pentium compatible processor is a 32-bit processor computer chip which supports the instructions in the IA-32 instruction set that were implemented by the Intel P5 Pentium processor family...

 cannot be plugged into a PCI Express
PCI Express
PCI Express , officially abbreviated as PCIe, is a computer expansion card standard designed to replace the older PCI, PCI-X, and AGP bus standards...

 bus. To expand the system, the proprietary front-side bus must connect through adapters for the various standard buses, like AGP
Accelerated Graphics Port
The Accelerated Graphics Port is a high-speed point-to-point channel for attaching a video card to a computer's motherboard, primarily to assist in the acceleration of 3D computer graphics. Since 2004 AGP has been progressively phased out in favor of PCI Express...

 or PCI Express. These are typically included in the respective controller functions, namely the northbridge
Northbridge (computing)
The northbridge has historically been one of the two chips in the core logic chipset on a PC motherboard, the other being the southbridge. Increasingly these functions have migrated to the CPU chip itself, beginning with memory and graphics controllers. For Intel Sandy Bridge and AMD Fusion...

and southbridge
Southbridge (computing)
The southbridge is one of the two chips in the core logic chipset on a personal computer motherboard, the other being the northbridge. The southbridge typically implements the slower capabilities of the motherboard in a northbridge/southbridge chipset computer architecture. In Intel chipset...

.

In contrast, HyperTransport is an open specification, published by a multi-company consortium. A single HyperTransport adapter chip will work with a wide spectrum of HyperTransport enabled microprocessors. For example, Broadcom HT-1000 and HT-2000 server controller devices can work with many different HyperTransport enabled microprocessors.

AMD uses HyperTransport to replace the Front-Side Bus
Front side bus
A front-side bus is a computer communication interface often used in computers during the 1990s and 2000s.It typically carries data between the central processing unit and a memory controller hub, known as the northbridge....

 in their Opteron
Opteron
Opteron is AMD's x86 server and workstation processor line, and was the first processor which supported the AMD64 instruction set architecture . It was released on April 22, 2003 with the SledgeHammer core and was intended to compete in the server and workstation markets, particularly in the same...

, Athlon 64
Athlon 64
The Athlon 64 is an eighth-generation, AMD64-architecture microprocessor produced by AMD, released on September 23, 2003. It is the third processor to bear the name Athlon, and the immediate successor to the Athlon XP...

, Sempron 64, Turion 64, Phenom
Phenom (processor)
Phenom is the 64-bit AMD desktop processor line based on the K10 microarchitecture, in what AMD calls family 10h processors, sometimes incorrectly called "K10h". Triple-core versions belong to the Phenom 8000 series and quad cores to the AMD Phenom X4 9000 series...

 and Phenom II
Phenom II
Phenom II is a family of AMD's multi-core 45 nm processors using the AMD K10 microarchitecture, succeeding the original Phenom. Advanced Micro Devices released the Socket AM2+ version of Phenom II in December 2008, while Socket AM3 versions with DDR3 support, along with an initial batch of...

 families of microprocessors.

Multiprocessor interconnect

Another use for HyperTransport is as an interconnect for NUMA
Non-Uniform Memory Access
Non-Uniform Memory Access is a computer memory design used in Multiprocessing, where the memory access time depends on the memory location relative to a processor...

 multiprocessor
Multiprocessor
Computer system having two or more processing units each sharing main memory and peripherals, in order to simultaneously process programs.Sometimes the term Multiprocessor is confused with the term Multiprocessing....

 computers. AMD uses HyperTransport with a proprietary cache coherency
Cache coherency
In computing, cache coherence refers to the consistency of data stored in local caches of a shared resource.When clients in a system maintain caches of a common memory resource, problems may arise with inconsistent data. This is particularly true of CPUs in a multiprocessing system...

 extension as part of their Direct Connect Architecture
Direct Connect Architecture
The Direct Connect Architecture is the I/O architecture of the Athlon 64 X2, Opteron, and Phenom microprocessors from AMD. It consists of the combination of three elements:...

 in their Opteron
Opteron
Opteron is AMD's x86 server and workstation processor line, and was the first processor which supported the AMD64 instruction set architecture . It was released on April 22, 2003 with the SledgeHammer core and was intended to compete in the server and workstation markets, particularly in the same...

 and Athlon 64 FX (Dual Socket Direct Connect (DSDC) Architecture) line of processors. The HORUS interconnect
AMD Horus
The Horus system, designed by Newisys for AMD, was created to enable AMD Opteron machines to extend beyond the current limit of 8-way architectures...

 from Newisys
Newisys
Newisys, a Server and Storage company with expertise in glue-chips for Opterons, based in Austin, Texas, was co-founded by Claymon A Cipione and Phil Hester in 2000, and was acquired in 2004 by manufacturer Sanmina-SCI...

 extends this concept to larger clusters. The Aqua device from 3Leaf Systems virtualizes and interconnects CPUs, memory, and I/O.

Router or switch bus replacement

HyperTransport can also be used as a bus in routers and switches
Network switch
A network switch or switching hub is a computer networking device that connects network segments.The term commonly refers to a multi-port network bridge that processes and routes data at the data link layer of the OSI model...

. Routers and switches have multiple network interfaces, and must forward data between these ports as fast as possible. For example, a four-port, 1000 Mbit
Megabit
The megabit is a multiple of the unit bit for digital information or computer storage. The prefix mega is defined in the International System of Units as a multiplier of 106 , and therefore...

/s Ethernet
Ethernet
Ethernet is a family of computer networking technologies for local area networks commercially introduced in 1980. Standardized in IEEE 802.3, Ethernet has largely replaced competing wired LAN technologies....

 router needs a maximum 8000 Mbit/s of internal bandwidth (1000 Mbit/s × 4 ports × 2 directions)—hyperTransport greatly exceeds the bandwidth this application requires.

Co-processor interconnect

The issue of latency and bandwidth between CPUs and co-processors has usually been the major stumbling block to their practical implementation. Recently, co-processors such as FPGAs have appeared that can access the HyperTransport bus and become first-class citizens on the motherboard. Current generation FPGAs from both main manufacturers (Altera
Altera
Altera Corporation is a Silicon Valley manufacturer of PLDs . The company offered its first programmable logic device in 1984. PLDs can be reprogrammed during the design cycle as well as in the field to perform multiple functions, and they support a fairly fast design process...

 and Xilinx
Xilinx
Xilinx, Inc. is a supplier of programmable logic devices. It is known for inventing the field programmable gate array and as the first semiconductor company with a fabless manufacturing model....

) directly support the HyperTransport interface, and have IP Cores
Semiconductor intellectual property core
In electronic design a semiconductor intellectual property core, IP core, or IP block is a reusable unit of logic, cell, or chip layout design that is the intellectual property of one party. IP cores may be licensed to another party or can be owned and used by a single party alone...

 available. Companies such as XtremeData, Inc. and DRC take these FPGAs (Xilinx in DRC's case) and create a module that allows FPGAs to plug directly into the Opteron socket.

AMD started an initiative named Torrenza
Torrenza
Torrenza was an initiative announced by Advanced Micro Devices in 2006 to improve support for the integration of specialized coprocessors in systems based on AMD Opteron microprocessors...

 on September 21, 2006 to further promote the usage of HyperTransport for plug-in cards and coprocessors. This initiative opened their "Socket F" to plug-in boards such as those from XtremeData and DRC.

Add-on card connector (HTX and HTX3)

A connector specification that allows a slot-based peripheral to have direct connection to a microprocessor using a HyperTransport interface was released by the HyperTransport Consortium. It is known as HyperTransport eXpansion (HTX). Using a rotated instance of the same mechanical connector as a 16-lane PCI-Express slot (plus an x1 connector for power pins), HTX allows development of plug-in cards that support direct access to a CPU and DMA
Direct memory access
Direct memory access is a feature of modern computers that allows certain hardware subsystems within the computer to access system memory independently of the central processing unit ....

 to the system RAM. The initial card for this slot was the QLogic
QLogic
QLogic Corporation is an Aliso Viejo, California-based designer and supplier of storage networking, high performance computing networking, and converged infrastructure solutions...

 InfiniPath InfiniBand HCA. IBM and HP
Hewlett-Packard
Hewlett-Packard Company or HP is an American multinational information technology corporation headquartered in Palo Alto, California, USA that provides products, technologies, softwares, solutions and services to consumers, small- and medium-sized businesses and large enterprises, including...

, among others, have released HTX compliant systems.

The original HTX standard is limited to 16 bits and 800 MHz.

In August 2008, the HyperTransport Consortium released HTX3, which extends the clock rate of HTX to 2.6 GHz (5.2 GT/s, 10.7 GTi, 5.2 real GHz data rate, 3 MT/s edit rate) and retains backwards compatibility.

Testing

The "DUT" test connector is defined to enable standardized functional test system interconnection.

Implementations

  • AMD AMD64 and Direct Connect Architecture
    Direct Connect Architecture
    The Direct Connect Architecture is the I/O architecture of the Athlon 64 X2, Opteron, and Phenom microprocessors from AMD. It consists of the combination of three elements:...

     based CPUs
    Central processing unit
    The central processing unit is the portion of a computer system that carries out the instructions of a computer program, to perform the basic arithmetical, logical, and input/output operations of the system. The CPU plays a role somewhat analogous to the brain in the computer. The term has been in...

  • SiByte MIPS
    MIPS architecture
    MIPS is a reduced instruction set computer instruction set architecture developed by MIPS Technologies . The early MIPS architectures were 32-bit, and later versions were 64-bit...

     cpus from Broadcom
    Broadcom
    Broadcom Corporation is a fabless semiconductor company in the wireless and broadband communication business. The company is headquartered in Irvine, California, USA. Broadcom was founded by a professor-student pair Henry Samueli and Henry T. Nicholas III from the University of California, Los...

  • PMC-Sierra
    PMC-Sierra
    PMC-Sierra is a fabless semiconductor company which develops and sells devices into the communications, storage, printing, and embedded computing marketplaces.-Corporate history:...

     RM9000X2 MIPS
    MIPS architecture
    MIPS is a reduced instruction set computer instruction set architecture developed by MIPS Technologies . The early MIPS architectures were 32-bit, and later versions were 64-bit...

     CPU
  • Raza Thread Processors
  • Loongson-3 MIPS
    MIPS architecture
    MIPS is a reduced instruction set computer instruction set architecture developed by MIPS Technologies . The early MIPS architectures were 32-bit, and later versions were 64-bit...

     processor
  • ht_tunnel from OpenCores
    OpenCores
    OpenCores is the world's largest open source hardware community developing digital open source hardware through electronic design automation, with a similar ethos to the free software movement. OpenCores hopes to eliminate redundant design work and slash development costs. A number of companies...

     project (MPL licence)
  • ATI
    ATI Technologies
    ATI Technologies Inc. was a semiconductor technology corporation based in Markham, Ontario, Canada, that specialized in the development of graphics processing units and chipsets. Founded in 1985 as Array Technologies Inc., the company was listed publicly in 1993 and was acquired by Advanced Micro...

     Radeon Xpress 200 for AMD Processor
  • Nvidia
    NVIDIA
    Nvidia is an American global technology company based in Santa Clara, California. Nvidia is best known for its graphics processors . Nvidia and chief rival AMD Graphics Techonologies have dominated the high performance GPU market, pushing other manufacturers to smaller, niche roles...

     nForce chipsets
    • nForce Professional MCPs (Media and Communication Processor)
    • nForce 4
      NForce4
      The nForce4 is a motherboard chipset released by Nvidia in October, 2004. The chipset supports AMD 64-bit processors and Intel Pentium 4 LGA 775 processors.-nForce4/nForce4-4x:...

       series
    • nForce 500 series
      NForce 500
      The nForce 500 is a motherboard chipset series and the successor to the nForce4 series. It was revealed by NVIDIA on 2006-03-07 and released on 2006-05-23...

    • nForce 600 series
      NForce 600
      The nForce 600 chipset was released in the first half of November 2006, coinciding with the GeForce 8 series launch on November 8, 2006. The nForce 600 supports Intel's LGA 775 socket and AMD's Quad FX platform and replaces the nForce 500 series....

    • nForce 700 series
      NForce 700
      The nForce 700 is a chipset series designed by Nvidia first released in December 2007. The series supports both Intel Core 2 and AMD Phenom processors, and replaces the nForce 600 series chipsets...

  • ServerWorks (now Broadcom) HyperTransport SystemI/O Controllers
    • HT-2000
    • HT-2100
  • The IBM
    IBM
    International Business Machines Corporation or IBM is an American multinational technology and consulting corporation headquartered in Armonk, New York, United States. IBM manufactures and sells computer hardware and software, and it offers infrastructure, hosting and consulting services in areas...

     CPC925 and CPC945 PowerPC 970 northbridges, as co-designed and used by Apple in the Power Mac G5
    Power Mac G5
    The Power Mac G5 is Apple's marketing name for models of the Power Macintosh that contains the IBM PowerPC G5 CPU. The professional-grade computer was the most powerful in Apple's lineup when it was introduced, widely hailed as the first 64-bit PC, and was touted by Apple as the fastest personal...

  • Several open source cores from the HyperTransport Center of Excellence

Frequency specifications

HyperTransport
version
Year Max. HT frequency Max. link width Max. aggregate bandwidth
(bi-directional)
Max. bandwidth at
16-bit unidirectional
Max. bandwidth at
32-bit unidirectional*
1.0 2001 800 MHz 32-bit 12.8 GB/s 3.2 GB/s 6.4 GB/s
1.1 2002 800 MHz 32-bit 12.8 GB/s 3.2 GB/s 6.4 GB/s
2.0 2004 1.4 GHz 32-bit 22.4 GB/s 5.6 GB/s 11.2 GB/s
3.0 2006 2.6 GHz 32-bit 41.6 GB/s 10.4 GB/s 20.8 GB/s
3.1 2008 3.2 GHz 32-bit 51.2 GB/s 12.8 GB/s 25.6 GB/s

  • AMD Athlon 64
    Athlon 64
    The Athlon 64 is an eighth-generation, AMD64-architecture microprocessor produced by AMD, released on September 23, 2003. It is the third processor to bear the name Athlon, and the immediate successor to the Athlon XP...

    , Athlon 64 FX, Athlon 64 X2
    Athlon 64 X2
    The Athlon 64 X2 is the first dual-core desktop CPU designed by AMD. It was designed from scratch as native dual-core by using an already multi-CPU enabled Athlon 64, joining it with another functional core on one die, and connecting both via a shared dual-channel memory controller/north bridge and...

    , Athlon X2, Athlon II
    Athlon II
    Athlon II is a family of AMD multi-core 45 nm central processing units, which is aimed at the midrange to budget market and is a complementary product lineup to the Phenom II.-Features:...

    , Phenom, Phenom II
    Phenom II
    Phenom II is a family of AMD's multi-core 45 nm processors using the AMD K10 microarchitecture, succeeding the original Phenom. Advanced Micro Devices released the Socket AM2+ version of Phenom II in December 2008, while Socket AM3 versions with DDR3 support, along with an initial batch of...

    , Sempron
    Sempron
    Sempron has been the marketing name used by AMD for several different budget desktop CPUs, using several different technologies and CPU socket formats. The Sempron replaced the AMD Duron processor and competes against Intel's Celeron series of processors...

    , Turion
    AMD Turion
    AMD Turion is the brand name AMD applies to its 64-bit low-power consumption processors codenamed K8L. The Turion 64 and Turion 64 X2/Ultra processors compete with Intel's mobile processors, initially the Pentium M and the Intel Core and Intel Core 2 processors.-Features:Earlier Turion 64...

     series and later use one 16-bit HyperTransport link. AMD Athlon64 FX (1207
    Socket F
    Socket F is a CPU socket designed by AMD for its Opteron line of CPUs released on August 15, 2006. In 2010 Socket F was replaced by Socket C32 for entry-level servers and Socket G34 for high-end servers.-Technical specifications:...

    ), Opteron
    Opteron
    Opteron is AMD's x86 server and workstation processor line, and was the first processor which supported the AMD64 instruction set architecture . It was released on April 22, 2003 with the SledgeHammer core and was intended to compete in the server and workstation markets, particularly in the same...

     use up to three 16-bit HyperTransport links. Common clock rates for these processor links are 800 MHz to 1 GHz (older single and multi socket systems on 754/939/940 links) and 1.6 GHz to 2.0 GHz (newer single socket systems on AM2+/AM3 links - most newer cpus using 2.0Ghz). While HyperTransport itself is capable of 32-bit width links, that width is not currently utilized by any AMD processors. Some chipsets though do not even utilize the 16-bit width used by the processors. Those include the Nvidia nForce3 150
    NForce3
    The nForce3 chipset was created by Nvidia as a Media and Communications Processor. Specifically, it was designed for use with the Athlon 64 processor.- Features of the nForce3 :...

    , nForce3 Pro 150
    NForce3
    The nForce3 chipset was created by Nvidia as a Media and Communications Processor. Specifically, it was designed for use with the Athlon 64 processor.- Features of the nForce3 :...

    , and the ULi
    Acer Laboratories Incorporated
    Acer Laboratories Incorporated is a major designer and manufacturer of integrated circuits for the personal computer and embedded systems markets. It is a subsidiary of the Acer group....

     M1689—which use a 16-bit HyperTransport downstream link but limit the HyperTransport upstream link to 8 bits.

Name

There has been some marketing confusion between the use of HT referring to HyperTransport and the later use of HT to refer to Intel's Hyper-Threading
Hyper-threading
Hyper-threading is Intel's term for its simultaneous multithreading implementation in its Atom, Intel Core i3/i5/i7, Itanium, Pentium 4 and Xeon CPUs....

 feature on some Pentium 4
Pentium 4
Pentium 4 was a line of single-core desktop and laptop central processing units , introduced by Intel on November 20, 2000 and shipped through August 8, 2008. They had a 7th-generation x86 microarchitecture, called NetBurst, which was the company's first all-new design since the introduction of the...

-based and the newer Nehalem and Westmere-based Intel Core
Intel Core
Yonah was the code name for Intel's first generation of 65 nm process mobile microprocessors, based on the Banias/Dothan-core Pentium M microarchitecture. SIMD performance has been improved through the addition of SSE3 instructions and improvements to SSE and SSE2 implementations, while integer...

 microprocessors. Hyper-Threading is officially known as Hyper-Threading Technology (HTT) or HT Technology. Because of this potential for confusion, the HyperTransport Consortium always uses the written-out form: "HyperTransport."

See also

  • Elastic interface bus
    Elastic interface bus
    Elastic Interface buses, abbreviated as EI bus connections, can be generalized as bus connections which are high speed interfaces that send clock signals with data.-Description:...

  • Fibre Channel
    Fibre Channel
    Fibre Channel, or FC, is a gigabit-speed network technology primarily used for storage networking. Fibre Channel is standardized in the T11 Technical Committee of the InterNational Committee for Information Technology Standards , an American National Standards Institute –accredited standards...

  • Front side bus
    Front side bus
    A front-side bus is a computer communication interface often used in computers during the 1990s and 2000s.It typically carries data between the central processing unit and a memory controller hub, known as the northbridge....

  • Intel QuickPath Interconnect
  • List of device bandwidths
  • PCI Express
    PCI Express
    PCI Express , officially abbreviated as PCIe, is a computer expansion card standard designed to replace the older PCI, PCI-X, and AGP bus standards...

  • RapidIO
    RapidIO
    The RapidIO architecture is a high-performance packet-switched, interconnect technology for interconnecting chips on a circuit board, and also circuit boards to each other using a backplane...


External links

The source of this article is wikipedia, the free encyclopedia.  The text of this article is licensed under the GFDL.
 
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