Elastic interface bus
Encyclopedia
Elastic Interface buses, abbreviated as EI bus connections, can be generalized as bus connections which are high speed interfaces that send clock signal
Clock signal
In electronics and especially synchronous digital circuits, a clock signal is a particular type of signal that oscillates between a high and a low state and is utilized like a metronome to coordinate actions of circuits...

s with data.

Description

The data bits that are sent through EI bus connections are aligned to the clock so that they latch to the data at the high speeds. EI bus connections require that the net topology
Topology
Topology is a major area of mathematics concerned with properties that are preserved under continuous deformations of objects, such as deformations that involve stretching, but no tearing or gluing...

 and timing characteristics for each net
Net (mathematics)
In mathematics, more specifically in general topology and related branches, a net or Moore–Smith sequence is a generalization of the notion of a sequence. In essence, a sequence is a function with domain the natural numbers, and in the context of topology, the range of this function is...

 on the bus are at least similar to each other in order to make lining up the edges of the data to the clock signals possible. In this environment, re-working connections in the connection module was not easily possible because all nets needed to have similar topology and timing characteristics. This increased the difficulty of a re-work solution or made it impossible and increased the modules
Multi-Chip Module
A multi-chip module is a specialized electronic package where multiple integrated circuits , semiconductor dies or other discrete components are packaged onto a unifying substrate, facilitating their use as a single component...

 that needed to be scrapped as unusable.

Repair

Elastic Interface repair involves a spare wire that is built into the bus interface in the connection module that has the same topology and characteristics of the rest of the nets in the bus. It includes hardware that is able to switch from the bad net in the interface to the spare net (as of now, this operation must be supported by the original manufacturer of the EI bus connector). The connection module is tested at several different process corners such as low and high temperature and low and high voltages. When a net on the interface is known to be bad, the spare net is used on the bus for testing and the bad net is not tested. When the bus does not have a defect, the spare net is tested with the functional nets. In the original design specification for the EI spare, the wire was driven with a constant zero when not used.

Applications

  • IBM
    IBM
    International Business Machines Corporation or IBM is an American multinational technology and consulting corporation headquartered in Armonk, New York, United States. IBM manufactures and sells computer hardware and software, and it offers infrastructure, hosting and consulting services in areas...

    , inventor of the elastic interface bus, uses it in many high end processors:
    • Elastic Interface (EI-1): POWER4
      POWER4
      The POWER4 is a microprocessor developed by International Business Machines that implemented the 64-bit PowerPC and PowerPC AS instruction set architectures. Released in 2001, the POWER4 succeeded the POWER3 and RS64 microprocessors, and was used in RS/6000 and AS/400 computers, ending a separate...

      , PowerPC 970
      PowerPC 970
      The PowerPC 970, PowerPC 970FX, PowerPC 970GX, and PowerPC 970MP, are 64-bit Power Architecture processors from IBM introduced in 2002. When used in Apple Inc. machines, they were dubbed the PowerPC G5....

       and Z900
    • Elastic Interface 2 (EI-2): POWER5
      POWER5
      The POWER5 is a microprocessor developed and fabricated by IBM. It is an improved version of the highly successful POWER4. The principal improvements are support for simultaneous multithreading and an on-die memory controller...

       and Z9
    • Elastic Interface 3 (EI-3): POWER6
      POWER6
      The POWER6 is a microprocessor developed by IBM that implemented the Power ISA v.2.03. When it became available in systems in 2007, it succeeded the POWER5+ as IBM's flagship Power microprocessor...

      , Z10
      IBM z10 (microprocessor)
      The z10 is a microprocessor chip made by IBM for their System z10 mainframe computers, released February 26, 2008. It was called "z6" during development.- Description :...

      , POWER7
      POWER7
      POWER7 is a Power Architecture microprocessor released in 2010 that succeeded the POWER6. POWER7 was developed by IBM at several sites including IBM's Rochester, MN; Austin, TX; Essex Junction, Vermont; T. J. Watson Research Center, NY; Bromont, QC and Böblingen, Germany laboratories...

      , PowerEN
      PowerPC A2
      The PowerPC A2 is a massively multicore capable and multithreaded 64-bit Power Architecture processor core designed by IBM using the Power ISA v.2.06 specification. Versions of processors based on the A2 core range from a 2.3 GHz version with 16 cores consuming 65 W to a less powerful, four core...

  • Mai Logic is a licensee of the Elastic Interface technology for PowerPC 970 applications.
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