Asynchronous systems
Encyclopedia
In a synchronous system, operations are coordinated under the
centralized control of a fixed-rate clock signal
or several clocks. An
asynchronous digital system, in contrast, has no global clock: instead,
it operates under distributed control, with concurrent hardware components
communicating and synchronizing
on channels
.
typically constructed out of modular 'hardware objects', each with
well-defined communication interface
s.
These modules
may operate at variable speeds, whether due to data-dependent processing,
dynamic voltage scaling
, or process variation. The modules can then be combined
together to form a correct working system, without reference to a global
clock signal
. Typically, low power is obtained since components are activated
only on demand. Furthermore, several asynchronous styles have been shown
to accommodate clocked interfaces, and thereby support mixed-timing design.
Hence, asynchronous systems match well the need for correct-by-construction
methodologies
in assembling large-scale heterogeneous and scalable systems.
between robustness and performance (and other parameters such
as power). The choice of design style depends on the application target:
reliability/ease-of-design vs. speed. The most robust designs use
'delay-insensitive circuits
', whose operation is correct regardless
of gate and wire delays
; however, only limited useful systems can be
designed with this style. Slightly less robust, but much more useful, are
'quasi-delay-insensitive circuits'
(also known as 'speed-independent'),
such as Delay Insensitive Minterm Synthesis
,
which operate correctly regardless of gate delays
; however, wires at
each fanout
point must be tuned for roughly equal delays. Less robust
but faster circuits, requiring simple localized one-sided timing constraints,
include controllers
using 'fundamental mode operation'
(i.e. with setup/hold requirements on when new inputs can be received), and 'bundled datapaths'
using matched delays (see below). At the extreme, high-performance
'timed circuits' have been proposed, which use tight two-side timing constraints,
where the clock
can still be avoided but careful physical
delay tuning is required, such as for some high-speed
pipeline applications.
is typically performed on channels
.
Communication is used both to synchronize operations of the concurrent
system as well as to pass data. A simple channel typically consists
of two wires: a request and an acknowledge. In a '4-phase handshaking
protocol' (or return-to-zero), the request is asserted by the sender
component, and the receiver responds by asserting the acknowledge;
then both signals are de-asserted in turn. In a '2-phase handshaking
protocol' (or transition-signalling), the requester simply toggles the
value on the request wire (once), and the receiver responds by toggling
the value on the acknowledge wire. Channels can also be extended to
communicate data.
s are typically encoded using several schemes.
Robust schemes use two wires or 'rails' for each bit, called 'dual-rail
encoding'. In this case, first rail is asserted
to transmit a 0 value,
or the second rail is asserted to transmit a 1 value. The asserted rail
is then reset to zero before the next data value is transmitted, thereby
indicating 'no data' or a 'spacer' state. A less robust, but widely-used
and practical scheme, is called 'single-rail bundled data'.
Here, a single-rail (i.e. synchronous-style) function block can be used, with
an accompanying worst-case matched delay. After valid data inputs arrive,
a request signal is asserted
as the input to the matched delay. When
the matched delay produces a 'done' output, the block guaranteed to have
completed computation. While this scheme has timing constraints, they
are simple, localized (unlike in synchronous systems),
and one-sided, hence are usually easy to validate.
and journal proceedings. The leading symposium is the IEEE Async Symposium
(International Symposium on Asynchronous Circuits and Systems), founded in
1994. A variety of asynchronous papers have also been published since the
mid-1980s in such conferences as IEEE/ACM Design Automation Conference
,
IEEE International Conference on Computer Design, IEEE/ACM
International Conference on Computer-Aided Design
,
International Solid-State Circuits Conference,
and Advanced Research in VLSI, as well as in leading journals
such as IEEE Transactions on VLSI Systems, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
, and Transactions on Distributed Computing.
centralized control of a fixed-rate clock signal
Clock signal
In electronics and especially synchronous digital circuits, a clock signal is a particular type of signal that oscillates between a high and a low state and is utilized like a metronome to coordinate actions of circuits...
or several clocks. An
asynchronous digital system, in contrast, has no global clock: instead,
it operates under distributed control, with concurrent hardware components
Electronic component
An electronic component is a basic electronic element and may be available in a discrete form having two or more electrical terminals . These are intended to be connected together, usually by soldering to a printed circuit board, in order to create an electronic circuit with a particular function...
communicating and synchronizing
Synchronizing
In telecommunication, the term synchronizing has the following meanings:# Achieving and maintaining synchronism.# In fax, achieving and maintaining predetermined speed relations between the scanning spot and the recording spot within each scanning line....
on channels
Channel (communications)
In telecommunications and computer networking, a communication channel, or channel, refers either to a physical transmission medium such as a wire, or to a logical connection over a multiplexed medium such as a radio channel...
.
Modularity
Asynchronous systems — much like object-oriented software — aretypically constructed out of modular 'hardware objects', each with
well-defined communication interface
Interface (computer science)
In the field of computer science, an interface is a tool and concept that refers to a point of interaction between components, and is applicable at the level of both hardware and software...
s.
These modules
Modularity (programming)
Modular programming is a software design technique that increases the extent to which software is composed of separate, interchangeable components called modules by breaking down program functions into modules, each of which accomplishes one function and contains everything necessary to accomplish...
may operate at variable speeds, whether due to data-dependent processing,
dynamic voltage scaling
Dynamic voltage scaling
Dynamic voltage scaling is a power management technique in computer architecture, where the voltage used in a component is increased or decreased, depending upon circumstances. Dynamic voltage scaling to increase voltage is known as overvolting; dynamic voltage scaling to decrease voltage is known...
, or process variation. The modules can then be combined
together to form a correct working system, without reference to a global
clock signal
Clock signal
In electronics and especially synchronous digital circuits, a clock signal is a particular type of signal that oscillates between a high and a low state and is utilized like a metronome to coordinate actions of circuits...
. Typically, low power is obtained since components are activated
only on demand. Furthermore, several asynchronous styles have been shown
to accommodate clocked interfaces, and thereby support mixed-timing design.
Hence, asynchronous systems match well the need for correct-by-construction
methodologies
Methodology
Methodology is generally a guideline for solving a problem, with specificcomponents such as phases, tasks, methods, techniques and tools . It can be defined also as follows:...
in assembling large-scale heterogeneous and scalable systems.
Design styles
There is a large spectrum of asynchronous design styles, with tradeoffsbetween robustness and performance (and other parameters such
as power). The choice of design style depends on the application target:
reliability/ease-of-design vs. speed. The most robust designs use
'delay-insensitive circuits
Delay insensitive circuit
A delay insensitive circuit is a type of asynchronous circuit which performs a logic operation often within a computing processor chip. Instead of using clock signals or other global control signals, the sequencing of computation in delay insensitive circuit is determined by the data...
', whose operation is correct regardless
of gate and wire delays
Delay calculation
Delay calculation is the term used in integrated circuit design for the calculation of the gate delay of a single logic gate and the wires attached to it. By contrast, static timing analysis computes the delays of entire paths, using delay calculation to determine the delay of each gate and...
; however, only limited useful systems can be
designed with this style. Slightly less robust, but much more useful, are
'quasi-delay-insensitive circuits'
Quasi Delay Insensitive
In digital logic design, Quasi Delay-Insensitive circuits are a class of almost delay-insensitive asynchronous circuits which are invariant to the delays of any of the circuit's wires or elements, except to assume that certain fanouts are isochronic...
(also known as 'speed-independent'),
such as Delay Insensitive Minterm Synthesis
Delay Insensitive Minterm Synthesis
Invented by David E. Muller, the DIMS system is an asynchronous design methodology making the least possible timing assumptions. Assuming only the Quasi-Delay-Insensitive delay model the generated designs need little if any timing hazard testing. The basis for DIMS is the use of two wires to...
,
which operate correctly regardless of gate delays
Delay calculation
Delay calculation is the term used in integrated circuit design for the calculation of the gate delay of a single logic gate and the wires attached to it. By contrast, static timing analysis computes the delays of entire paths, using delay calculation to determine the delay of each gate and...
; however, wires at
each fanout
Fanout
In digital electronics, the fan-out of a logic gate output is the number of gate inputs to which it is connected.In most designs, logic gates are connected together to form more complex circuits. While no more than one logic gate output is connected to any single input, it is common for one output...
point must be tuned for roughly equal delays. Less robust
but faster circuits, requiring simple localized one-sided timing constraints,
include controllers
Controller (computing)
In computing and especially in computer hardware, controller is a chip, an expansion card, or a stand-alone device that interfaces with a peripheral device...
using 'fundamental mode operation'
(i.e. with setup/hold requirements on when new inputs can be received), and 'bundled datapaths'
using matched delays (see below). At the extreme, high-performance
'timed circuits' have been proposed, which use tight two-side timing constraints,
where the clock
Clock signal
In electronics and especially synchronous digital circuits, a clock signal is a particular type of signal that oscillates between a high and a low state and is utilized like a metronome to coordinate actions of circuits...
can still be avoided but careful physical
delay tuning is required, such as for some high-speed
pipeline applications.
Asynchronous communication
Asynchronous communicationAsynchronous communication
In telecommunications, asynchronous communication is transmission of data without the use of an external clock signal, where data can be transmitted intermittently rather than in a steady stream. Any timing required to recover data from the communication symbols is encoded within the symbols...
is typically performed on channels
Channel (communications)
In telecommunications and computer networking, a communication channel, or channel, refers either to a physical transmission medium such as a wire, or to a logical connection over a multiplexed medium such as a radio channel...
.
Communication is used both to synchronize operations of the concurrent
system as well as to pass data. A simple channel typically consists
of two wires: a request and an acknowledge. In a '4-phase handshaking
Handshaking
In information technology, telecommunications, and related fields, handshaking is an automated process of negotiation that dynamically sets parameters of a communications channel established between two entities before normal communication over the channel begins...
protocol' (or return-to-zero), the request is asserted by the sender
component, and the receiver responds by asserting the acknowledge;
then both signals are de-asserted in turn. In a '2-phase handshaking
Handshaking
In information technology, telecommunications, and related fields, handshaking is an automated process of negotiation that dynamically sets parameters of a communications channel established between two entities before normal communication over the channel begins...
protocol' (or transition-signalling), the requester simply toggles the
value on the request wire (once), and the receiver responds by toggling
the value on the acknowledge wire. Channels can also be extended to
communicate data.
Asynchronous datapaths
Asynchronous datapathDatapath
A datapath is a collection of functional units, such as arithmetic logic units or multipliers, that perform data processing operations. Most central processing units consist of a datapath and a control unit, with a large part of the control unit dedicated to regulating the interaction between the...
s are typically encoded using several schemes.
Robust schemes use two wires or 'rails' for each bit, called 'dual-rail
encoding'. In this case, first rail is asserted
Assertion
The term assertion has several meanings:* Assertion , a computer programming technique* Logical assertion, logical assertion of a statement* Proof by assertion, an assertion as opposed to an argument...
to transmit a 0 value,
or the second rail is asserted to transmit a 1 value. The asserted rail
is then reset to zero before the next data value is transmitted, thereby
indicating 'no data' or a 'spacer' state. A less robust, but widely-used
and practical scheme, is called 'single-rail bundled data'.
Here, a single-rail (i.e. synchronous-style) function block can be used, with
an accompanying worst-case matched delay. After valid data inputs arrive,
a request signal is asserted
Assertion
The term assertion has several meanings:* Assertion , a computer programming technique* Logical assertion, logical assertion of a statement* Proof by assertion, an assertion as opposed to an argument...
as the input to the matched delay. When
the matched delay produces a 'done' output, the block guaranteed to have
completed computation. While this scheme has timing constraints, they
are simple, localized (unlike in synchronous systems),
and one-sided, hence are usually easy to validate.
Literature
The literature in this field exists in a variety of conferenceand journal proceedings. The leading symposium is the IEEE Async Symposium
(International Symposium on Asynchronous Circuits and Systems), founded in
1994. A variety of asynchronous papers have also been published since the
mid-1980s in such conferences as IEEE/ACM Design Automation Conference
Design Automation Conference
The Design Automation Conference, or DAC, is a combination of a technical conference and a trade show, both specializing in electronic design automation....
,
IEEE International Conference on Computer Design, IEEE/ACM
International Conference on Computer-Aided Design
International Conference on Computer-Aided Design
The International Conference on Computer-Aided Design, or ICCAD, is a yearly conference about electronic design automation. It is normally held in early November in San Jose, California...
,
International Solid-State Circuits Conference,
and Advanced Research in VLSI, as well as in leading journals
such as IEEE Transactions on VLSI Systems, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, often abbreviated IEEE TCAD or IEEE Transactions on CAD, is a technical journal devoted to the design, analysis, and use of computer programs that aid in the design of integrated circuits and systems...
, and Transactions on Distributed Computing.
See also
- Asynchronous circuitAsynchronous circuitAn asynchronous circuit is a circuit in which the parts are largely autonomous. They are not governed by a clock circuit or global clock signal, but instead need only wait for the signals that indicate completion of instructions and operations. These signals are specified by simple data transfer...
- Integrated circuit designIntegrated circuit designIntegrated circuit design, or IC design, is a subset of electrical engineering and computer engineering, encompassing the particular logic and circuit design techniques required to design integrated circuits, or ICs...
- Electronic design automationElectronic design automationElectronic design automation is a category of software tools for designing electronic systems such as printed circuit boards and integrated circuits...
- Design flow (EDA)Design flow (EDA)Design flows are the explicit combination of electronic design automation tools to accomplish the design of an integrated circuit. Moore's law has driven the entire IC implementation RTL to GDSII design flows from one which uses primarily...
- perfect clock gating