In digital logic design, Quasi Delay-Insensitive (QDI) circuits are a class of almost delay-insensitive asynchronous circuit

Asynchronous circuit

An asynchronous circuit is a circuit in which the parts are largely autonomous. They are not governed by a clock circuit or global clock signal, but instead need only wait for the signals that indicate completion of instructions and operations. These signals are specified by simple data transfer...

s which are invariant to (and make no assumptions about) the delays of any of the circuit's wires or elements, except to assume that certain fanout

Fanout

In digital electronics, the fan-out of a logic gate output is the number of gate inputs to which it is connected.In most designs, logic gates are connected together to form more complex circuits. While no more than one logic gate output is connected to any single input, it is common for one output...

s are isochronic. Isochronic forks allow signals to travel to two destinations and only receive an acknowledge from one.

More importantly, QDI circuits are Turing-complete, while purely delay-insensitive circuits are not. Of all "useful" asynchronous design styles, QDI circuits make the fewest timing assumptions, as only the isochronic fork is assumed. In practice ensuring the correctness of an isochronic fork is trivial.

Two common design styles of QDI circuits are Delay Insensitive Minterm Synthesis

Delay Insensitive Minterm Synthesis

Invented by David E. Muller, the DIMS system is an asynchronous design methodology making the least possible timing assumptions. Assuming only the Quasi-Delay-Insensitive delay model the generated designs need little if any timing hazard testing. The basis for DIMS is the use of two wires to...

 (DIMS) and Pre-Charge Half Buffers based circuits.

Technically, QDI circuits are the same class of circuits as speed-independent circuits. The main difference between speed-independent and QDI circuits is that in QDI circuits, the designer is concerned with the acknowledgment of each transition, whereas in speed-independent design, the correctness of the isochronic assumption on each circuit node is assumed to be true and no distinction is made between circuit nodes that are isochronic forks and those that are not.

Manufactured QDI processor designs include: TITAC from Tokyo Institute of Technology, MiniMIPS from Caltech, SPA from The University of Manchester and ASPRO-216 from France Telecom. The first QDI processor was the Caltech asynchronous microprocessor of 1989 (a predecessor to the MiniMIPS processor).

Isochronic fork

An isochronic fork is a concept in asynchronous digital design.
Isochronic forks are forks in wires where if the acknowledging target has seen a transition on their end of the fork then the transition is assumed to have also happened on the other end of the fork too. There are two types of isochronic forks; the asymmetric types only ensure that the signal will reach the acknowledging fork tip before, or at the same time as, it will at the other fork tip, while the symmetric type ensures that both fork tips will be reached at the same time. Symmetrical isochronic forks allow either of the targets to acknowledge the signal. In quasi delay-insensitive (QDI) circuit

Electronic circuit

An electronic circuit is composed of individual electronic components, such as resistors, transistors, capacitors, inductors and diodes, connected by conductive wires or traces through which electric current can flow...

s all forks have to be either isochronic and acknowledged by one of the destinations, or acknowledged by all destinations. The concept of isochronic fork was introduced by A. J. Martin exactly to distinguish between asynchronous circuits that satisfy QDI requirements and those that do
not. Martin also established that given reasonable assumptions on the kinds of circuit elements
that are available to design with, it is impossible to design interesting systems without including
at least some asynchronic forks. Isochronic forks are in some sense the weakest compromise away from
fully delay-insensitive systems.