Asynchronous circuit
Encyclopedia
An asynchronous circuit is a circuit
in which the parts are largely autonomous. They are not governed by a clock circuit or global clock signal
, but instead need only wait for the signals that indicate completion of instructions and operations. These signals are specified by simple data transfer protocols. This digital logic design is contrasted with a synchronous circuit
which operates according to clock timing signals.
s are an attractive and powerful model for reasoning about asynchronous circuits. However Petri nets have been criticized for their lack of physical realism (see Petri net). Subsequent to Petri nets other models of concurrency have been developed that can model asynchronous circuits including the Actor model
and process calculi.
The term asynchronous logic is used to describe a variety of design styles, which use different assumptions about circuit properties. These vary from the bundled delay model - which uses 'conventional' data processing elements with completion indicated by a locally generated delay model - to delay-insensitive design - where arbitrary delays through circuit elements can be accommodated. The latter style tends to yield circuits which are larger than bundled data implementations, but which are insensitive to layout and parametric variations and are thus "correct by design".
Asynchronous logic is the logic
required for the design of asynchronous digital systems. These function without a clock signal
and so individual logic elements cannot be relied upon to have a discrete true/false state at any given time. Boolean logic
is inadequate for this and so extensions are required. Karl Fant developed a theoretical treatment of this in his work Logically determined design in 2005 which used four-valued logic
with null and intermediate being the additional values. Vadim Vasyukevich developed a different approach based upon a new logical operation which he called venjunction. This takes into account not only the current value of an element, but also its history.
(QDI) circuits, generally agreed to be the most "pure" form of asynchronous logic that retains computational universality. Less pure forms of asynchronous circuitry offer better performance at the cost of compromising one or more of these advantages:
Unlike a conventional processor, a clockless processor (asynchronous CPU) has no central clock to coordinate the progress of data through the pipeline.
Instead, stages of the CPU are coordinated using logic devices called "pipeline controls" or "FIFO sequencers." Basically, the pipeline controller clocks the next stage of logic when the existing stage is complete. In this way, a central clock is unnecessary. It may actually be even easier to implement high performance devices in asynchronous, as opposed to clocked, logic:
Asynchronous logic proponents believe these capabilities would have these benefits:
The biggest disadvantage of the clockless CPU is that most CPU design
tools assume a clocked CPU (i.e., a synchronous circuit
). Many tools "enforce synchronous design practices". Making a clockless CPU (designing an asynchronous circuit) involves modifying the design tools to handle clockless logic and doing extra testing to ensure the design avoids metastable
problems. The group that designed the AMULET, for example, developed a tool called LARD to cope with the complex design of AMULET3.
Despite the difficulty of doing so, numerous asynchronous CPUs have been built, including:
The ILLIAC II
was the first completely asynchronous, speed independent processor design ever built; it was the most powerful computer at the time.
DEC PDP-16 Register Transfer Modules (ca. 1973) allowed the experimenter to construct asynchronous, 16-bit processing elements. Delays for each module were fixed and based on the module's worst-case timing.
The Caltech Asynchronous Microprocessor (1988) was the first asynchronous microprocessor (1988). Caltech designed and manufactured the world's first fully Quasi Delay Insensitive
processor. During demonstrations, the researchers amazed viewers by loading a simple program which ran in a tight loop, pulsing one of the output lines after each instruction. This output line was connected to an oscilloscope. When a cup of hot coffee was placed on the chip, the pulse rate (the effective "clock rate") naturally slowed down to adapt to the worsening performance of the heated transistors. When liquid nitrogen
was poured on the chip, the instruction rate shot up with no additional intervention. Additionally, at lower temperatures, the voltage supplied to the chip could be safely increased, which also improved the instruction rate—again, with no additional configuration.
In 2004, Epson manufactured the world's first bendable microprocessor called ACT11, an 8-bit asynchronous chip.
Synchronous flexible processors are slower, since bending the material on which a chip is fabricated causes wild and unpredictable variations in the delays of various transistors, for which worst case scenarios must be assumed everywhere and everything must be clocked at worst case speed. The processor is intended for use in smart cards, whose chips are currently limited in size to those small enough that they can remain perfectly rigid.
Electrical network
An electrical network is an interconnection of electrical elements such as resistors, inductors, capacitors, transmission lines, voltage sources, current sources and switches. An electrical circuit is a special type of network, one that has a closed loop giving a return path for the current...
in which the parts are largely autonomous. They are not governed by a clock circuit or global clock signal
Clock signal
In electronics and especially synchronous digital circuits, a clock signal is a particular type of signal that oscillates between a high and a low state and is utilized like a metronome to coordinate actions of circuits...
, but instead need only wait for the signals that indicate completion of instructions and operations. These signals are specified by simple data transfer protocols. This digital logic design is contrasted with a synchronous circuit
Synchronous circuit
A synchronous circuit is a digital circuit in which the parts are synchronized by a clock signal.In an ideal synchronous circuit, every change in the logical levels of its storage components is simultaneous. These transitions follow the level change of a special signal called the clock...
which operates according to clock timing signals.
Theoretical foundations
Petri netPetri net
A Petri net is one of several mathematical modeling languages for the description of distributed systems. A Petri net is a directed bipartite graph, in which the nodes represent transitions and places...
s are an attractive and powerful model for reasoning about asynchronous circuits. However Petri nets have been criticized for their lack of physical realism (see Petri net). Subsequent to Petri nets other models of concurrency have been developed that can model asynchronous circuits including the Actor model
Actor model
In computer science, the Actor model is a mathematical model of concurrent computation that treats "actors" as the universal primitives of concurrent digital computation: in response to a message that it receives, an actor can make local decisions, create more actors, send more messages, and...
and process calculi.
The term asynchronous logic is used to describe a variety of design styles, which use different assumptions about circuit properties. These vary from the bundled delay model - which uses 'conventional' data processing elements with completion indicated by a locally generated delay model - to delay-insensitive design - where arbitrary delays through circuit elements can be accommodated. The latter style tends to yield circuits which are larger than bundled data implementations, but which are insensitive to layout and parametric variations and are thus "correct by design".
Asynchronous logic is the logic
Logic
In philosophy, Logic is the formal systematic study of the principles of valid inference and correct reasoning. Logic is used in most intellectual activities, but is studied primarily in the disciplines of philosophy, mathematics, semantics, and computer science...
required for the design of asynchronous digital systems. These function without a clock signal
Clock signal
In electronics and especially synchronous digital circuits, a clock signal is a particular type of signal that oscillates between a high and a low state and is utilized like a metronome to coordinate actions of circuits...
and so individual logic elements cannot be relied upon to have a discrete true/false state at any given time. Boolean logic
Boolean logic
Boolean algebra is a logical calculus of truth values, developed by George Boole in the 1840s. It resembles the algebra of real numbers, but with the numeric operations of multiplication xy, addition x + y, and negation −x replaced by the respective logical operations of...
is inadequate for this and so extensions are required. Karl Fant developed a theoretical treatment of this in his work Logically determined design in 2005 which used four-valued logic
Multi-valued logic
In logic, a many-valued logic is a propositional calculus in which there are more than two truth values. Traditionally, in Aristotle's logical calculus, there were only two possible values for any proposition...
with null and intermediate being the additional values. Vadim Vasyukevich developed a different approach based upon a new logical operation which he called venjunction. This takes into account not only the current value of an element, but also its history.
Benefits
Different classes of asynchronous circuitry offer different advantages. Below is a list of the advantages offered by Quasi Delay InsensitiveQuasi Delay Insensitive
In digital logic design, Quasi Delay-Insensitive circuits are a class of almost delay-insensitive asynchronous circuits which are invariant to the delays of any of the circuit's wires or elements, except to assume that certain fanouts are isochronic...
(QDI) circuits, generally agreed to be the most "pure" form of asynchronous logic that retains computational universality. Less pure forms of asynchronous circuitry offer better performance at the cost of compromising one or more of these advantages:
- Robust handling of metastabilityMetastability in electronicsMetastability in electronics is the ability of a digital electronic system to persist for an unbounded time in an unstable equilibrium or metastable state....
of arbitersArbiter (electronics)-Asynchronous arbiters:An important form of arbiter is used in asynchronous circuits, to select the order of access to a shared resource among asynchronous requests. Its function is to prevent two operations from occurring at once when they should not...
. - Early completionEarly completionEarly completion is a property of some classes of asynchronous circuit. It means that the output of a circuit may be available as soon as sufficient inputs have arrived to allow it to be determined. For example, if all of the inputs to a mux have arrived, and all are the same, but the select line...
of a circuit when it is known that the inputs which have not yet arrived are irrelevant. - 70% lower power consumption compared to synchronous design
- Possibly lower power consumption because no transistor ever transitions unless it is performing useful computation (clock gatingClock gatingClock gating is a power-saving technique used in many synchronous circuits-Description:Clock gating is a popular technique used in many synchronous circuits for reducing dynamic power dissipation. Clock gating saves power by adding more logic to a circuit to prune the clock tree...
in synchronous designs is an imperfect approximation of this ideal). Also, clock drivers can be removed which can significantly reduce power consumption. However, when using certain encodings, asynchronous circuits may require more area, which can result in increased power consumption if the underlying process has poor leakage properties (for example, deep submicrometer processes used prior to the introduction of High-k dielectricHigh-k DielectricThe term high-κ dielectric refers to a material with a high dielectric constant κ used in semiconductor manufacturing processes which replaces the silicon dioxide gate dielectric...
s). - Freedom from the ever-worsening difficulties of distributing a high-fan-out, timing-sensitive clock signal.
- Better modularity and composability.
- Far fewer assumptions about the manufacturing process are required (most assumptions are timing assumptions).
- Circuit speed adapts to changing temperature and voltage conditions rather than being locked at the speed mandated by worst-case assumptions.
- Immunity to transistor-to-transistor variability in the manufacturing process, which is one of the most serious problems facing the semiconductor industry as dies shrink.
- Less severe electromagnetic interferenceElectromagnetic interferenceElectromagnetic interference is disturbance that affects an electrical circuit due to either electromagnetic induction or electromagnetic radiation emitted from an external source. The disturbance may interrupt, obstruct, or otherwise degrade or limit the effective performance of the circuit...
(EMI). Synchronous circuits create a great deal of EMI in the frequency band at (or very near) their clock frequency and its harmonics; asynchronous circuits generate EMI patterns which are much more evenly spread across the spectrum. - In asynchronous circuits, local signaling eliminates the need for global synchronization which exploits some potential advantages in comparison with synchronous ones. They have shown potential specifications in low power consumption, design reuse, improved noise immunity and electromagnetic compatibility. Asynchronous circuits are more tolerant to process variations and external voltage fluctuationshttp://ceit.aut.ac.ir/~ghavami/publications.htm.
- Less stress on the power distribution network. Synchronous circuits tend to draw a large amount of current right at the clock edge and shortly thereafter. The number of nodes switching (and thence, amount of current drawn) drops off rapidly after the clock edge, reaching zero just before the next clock edge. In an asynchronous circuit, the switching times of the nodes are not correlated in this manner, so the current draw tends to be more uniform and less bursty.
Disadvantages
- Hardware effort may be up to double the number of circuit elements (transistors), depending on level.
- Serial designs benefit more than massively parallel ones.
- Requires people experienced in synchronous design to learn a new style.
- Synchronous designs are inherently easier to debug than asynchronous designs.
- Performance analysis of asynchronous circuits may be challenging.
Asynchronous CPU
Asynchronous CPUs are one of several ideas for radically changing CPU design.Unlike a conventional processor, a clockless processor (asynchronous CPU) has no central clock to coordinate the progress of data through the pipeline.
Instead, stages of the CPU are coordinated using logic devices called "pipeline controls" or "FIFO sequencers." Basically, the pipeline controller clocks the next stage of logic when the existing stage is complete. In this way, a central clock is unnecessary. It may actually be even easier to implement high performance devices in asynchronous, as opposed to clocked, logic:
- components can run at different speeds on an asynchronous CPU; all major components of a clocked CPU must remain synchronized with the central clock;
- a traditional CPU cannot "go faster" than the expected worst-case performance of the slowest stage/instruction/component. When an asynchronous CPU completes an operation more quickly than anticipated, the next stage can immediately begin processing the results, rather than waiting for synchronization with a central clock. An operation might finish faster than normal because of attributes of the data being processed (e.g., multiplication can be very fast when multiplying by 0 or 1, even when running code produced by a naive compiler), or because of the presence of a higher voltage or bus speed setting, or a lower ambient temperature, than 'normal' or expected.
Asynchronous logic proponents believe these capabilities would have these benefits:
- lower power dissipation for a given performance level, and
- highest possible execution speeds.
The biggest disadvantage of the clockless CPU is that most CPU design
CPU design
CPU design is the design engineering task of creating a central processing unit , a component of computer hardware. It is a subfield of electronics engineering and computer engineering.- Overview :CPU design focuses on these areas:...
tools assume a clocked CPU (i.e., a synchronous circuit
Synchronous circuit
A synchronous circuit is a digital circuit in which the parts are synchronized by a clock signal.In an ideal synchronous circuit, every change in the logical levels of its storage components is simultaneous. These transitions follow the level change of a special signal called the clock...
). Many tools "enforce synchronous design practices". Making a clockless CPU (designing an asynchronous circuit) involves modifying the design tools to handle clockless logic and doing extra testing to ensure the design avoids metastable
Metastability in electronics
Metastability in electronics is the ability of a digital electronic system to persist for an unbounded time in an unstable equilibrium or metastable state....
problems. The group that designed the AMULET, for example, developed a tool called LARD to cope with the complex design of AMULET3.
Despite the difficulty of doing so, numerous asynchronous CPUs have been built, including:
- the ORDVACORDVACThe ORDVAC or Ordnance Discrete Variable Automatic Computer, an early computer built by the University of Illinois for the Ballistics Research Laboratory at Aberdeen Proving Ground, was based on the IAS architecture developed by John von Neumann, which came to be known as the von Neumann architecture...
and the (identical) ILLIAC IILLIAC IThe ILLIAC I , a pioneering computer built in 1952 by the University of Illinois, was the first computer built and owned entirely by a US educational institution, Manchester University UK having built Manchester Mark 1 in 1948.ILLIAC I was based on the Institute for Advanced Study Von Neumann...
(1951) - the WEIZACWEIZACThe WEIZAC was the first computer in Israel, and one of the first large-scale, stored-program, electronic computers in the world....
(1955) - the ILLIAC IIILLIAC IIThe ILLIAC II was a revolutionary super-computer built by the University of Illinois that became operational in 1962.-Description:The concept, proposed in 1958, pioneered Emitter-coupled logic circuitry, pipelining, and transistor memory with a design goal of 100x speedup compared to ILLIAC...
(1962)
- The Victoria University of ManchesterVictoria University of ManchesterThe Victoria University of Manchester was a university in Manchester, England. On 1 October 2004 it merged with the University of Manchester Institute of Science and Technology to form a new entity, "The University of Manchester".-1851 - 1951:The University was founded in 1851 as Owens College,...
built AtlasAtlas Computer (Manchester)The Atlas Computer was a joint development between the University of Manchester, Ferranti, and Plessey. The first Atlas, installed at Manchester University and officially commissioned in 1962, was one of the world's first supercomputers, considered to be the most powerful computer in the world at...
- The HoneywellHoneywellHoneywell International, Inc. is a major conglomerate company that produces a variety of consumer products, engineering services, and aerospace systems for a wide variety of customers, from private consumers to major corporations and governments....
CPUs 6180 (1972) and Series 60 Level 68 (1981) upon which MulticsMulticsMultics was an influential early time-sharing operating system. The project was started in 1964 in Cambridge, Massachusetts...
ran asynchronously
- The Caltech Asynchronous Microprocessor, the world-first asynchronous microprocessor (1988);
- the ARMARM architectureARM is a 32-bit reduced instruction set computer instruction set architecture developed by ARM Holdings. It was named the Advanced RISC Machine, and before that, the Acorn RISC Machine. The ARM architecture is the most widely used 32-bit ISA in numbers produced...
-implementing AMULETAMULET microprocessorAMULET is a series of microprocessors that implement the ARM processor architecture. Developed by the group under the University of Manchester's computer science school , AMULET is unique from other ARM implementations in being an asynchronous microprocessor, not making use of a square wave clock...
(1993 and 2000); - the asynchronous implementation of MIPSMIPS architectureMIPS is a reduced instruction set computer instruction set architecture developed by MIPS Technologies . The early MIPS architectures were 32-bit, and later versions were 64-bit...
R3000, dubbed MiniMIPS (1998); - several versions of the XAP processorXAP processorThe XAP processor is a RISC processor architecture developed by Cambridge Consultants Ltd since 1994. XAP processors are a family of 16-bit and 32-bit cores, all of which are intended for use in an application-specific integrated circuit or ASIC chip design...
experimented with different asynchronous design styles: a bundled data XAP, a 1-of-4 XAP, and a 1-of-2 (dual-rail) XAP (2003?); - an ARM-compatible processor (2003?) designed by Z. C. Yu, S. B. Furber, and L. A. Plana; "designed specifically to explore the benefits of asynchronous design for security sensitive applications";
- the "Network-based Asynchronous Architecture" processor (2005) that executes a subset of the MIPS architectureMIPS architectureMIPS is a reduced instruction set computer instruction set architecture developed by MIPS Technologies . The early MIPS architectures were 32-bit, and later versions were 64-bit...
instruction set; - the HT80C51 processor (2007???) from Handshake Solutions
- the SEAforth multi-core processor (2008) from Charles H. MooreCharles H. MooreCharles H. Moore is the inventor of the Forth programming language.- Biography :In 1968, while employed at the United States National Radio Astronomy Observatory , Moore invented the initial version of the Forth language to help control radio telescopes...
. - the GA144 multi-core processor (2010) from Charles H. MooreCharles H. MooreCharles H. Moore is the inventor of the Forth programming language.- Biography :In 1968, while employed at the United States National Radio Astronomy Observatory , Moore invented the initial version of the Forth language to help control radio telescopes...
.
The ILLIAC II
ILLIAC II
The ILLIAC II was a revolutionary super-computer built by the University of Illinois that became operational in 1962.-Description:The concept, proposed in 1958, pioneered Emitter-coupled logic circuitry, pipelining, and transistor memory with a design goal of 100x speedup compared to ILLIAC...
was the first completely asynchronous, speed independent processor design ever built; it was the most powerful computer at the time.
DEC PDP-16 Register Transfer Modules (ca. 1973) allowed the experimenter to construct asynchronous, 16-bit processing elements. Delays for each module were fixed and based on the module's worst-case timing.
The Caltech Asynchronous Microprocessor (1988) was the first asynchronous microprocessor (1988). Caltech designed and manufactured the world's first fully Quasi Delay Insensitive
Quasi Delay Insensitive
In digital logic design, Quasi Delay-Insensitive circuits are a class of almost delay-insensitive asynchronous circuits which are invariant to the delays of any of the circuit's wires or elements, except to assume that certain fanouts are isochronic...
processor. During demonstrations, the researchers amazed viewers by loading a simple program which ran in a tight loop, pulsing one of the output lines after each instruction. This output line was connected to an oscilloscope. When a cup of hot coffee was placed on the chip, the pulse rate (the effective "clock rate") naturally slowed down to adapt to the worsening performance of the heated transistors. When liquid nitrogen
Liquid nitrogen
Liquid nitrogen is nitrogen in a liquid state at a very low temperature. It is produced industrially by fractional distillation of liquid air. Liquid nitrogen is a colourless clear liquid with density of 0.807 g/mL at its boiling point and a dielectric constant of 1.4...
was poured on the chip, the instruction rate shot up with no additional intervention. Additionally, at lower temperatures, the voltage supplied to the chip could be safely increased, which also improved the instruction rate—again, with no additional configuration.
In 2004, Epson manufactured the world's first bendable microprocessor called ACT11, an 8-bit asynchronous chip.
Synchronous flexible processors are slower, since bending the material on which a chip is fabricated causes wild and unpredictable variations in the delays of various transistors, for which worst case scenarios must be assumed everywhere and everything must be clocked at worst case speed. The processor is intended for use in smart cards, whose chips are currently limited in size to those small enough that they can remain perfectly rigid.
External links
- TiDE from Handshakesolutions in The Netherlands, Commercial asynchronous circuits design tool. Commercial asynchronous ARM(ARM996HS) and 8051(HT80C51) are available.
- An introduction to asynchronous circuit design by Davis and Nowick
- Asynchronous logic elements. Venjunction and sequention by V. O. Vasyukevich
- Null convention logic, a design style pioneered by Theseus Logic, who have fabricated over 20 ASICs based on their NCL08 and NCL8501 microcontroller cores http://scism.sbu.ac.uk/ccsv/ACiD-WG/AsyncIndustryStatus.pdf
- The Status of Asynchronous Design in Industry Information Society Technologies (IST) Programme, IST-1999-29119, D. A. Edwards W. B. Toms, June 2004, via www.scism.lsbu.ac.uk
- The Red Star is a version of the MIPS R3000 implemented in asynchronous logic
- The Amulet microprocessors were asynchronous ARMs, built in the 1990s at University of ManchesterUniversity of ManchesterThe University of Manchester is a public research university located in Manchester, United Kingdom. It is a "red brick" university and a member of the Russell Group of research-intensive British universities and the N8 Group...
, England - The N-Protocol developed by Navarre AsyncArt, the first commercial asynchronous design methodology for conventional FPGAs.
- PGPSALM an asynchronous implementation of the 6502 microprocessor
- Caltech Async Group home page
- Tiempo: Fench company providing asynchronous IP and design tools
- Epson ACT11 Flexible CPU Press Release
- Amirkabir University of Technology (Iran) asynchronous publications, FPGA, SystemC