Soft microprocessor - AbsoluteAstronomy.com

A soft microprocessor is a microprocessor

Microprocessor

A microprocessor incorporates the functions of a computer's central processing unit on a single integrated circuit, or at most a few integrated circuits. It is a multipurpose, programmable device that accepts digital data as input, processes it according to instructions stored in its memory, and...

core that can be wholly implemented using logic synthesis

Logic synthesis

In electronics, logic synthesis is a process by which an abstract form of desired circuit behavior, typically register transfer level , is turned into a design implementation in terms of logic gates. Common examples of this process include synthesis of HDLs, including VHDL and Verilog...

. It can be implemented via different semiconductor

Semiconductor

A semiconductor is a material with electrical conductivity due to electron flow intermediate in magnitude between that of a conductor and an insulator. This means a conductivity roughly in the range of 103 to 10−8 siemens per centimeter...

devices containing programmable logic (e.g., ASIC

Application-specific integrated circuit

An application-specific integrated circuit is an integrated circuit customized for a particular use, rather than intended for general-purpose use. For example, a chip designed solely to run a cell phone is an ASIC...

, FPGA

Field-programmable gate array

A field-programmable gate array is an integrated circuit designed to be configured by the customer or designer after manufacturing—hence "field-programmable"...

, CPLD), including both high-end and commodity variations.

Most systems, if they use a soft processor at all, only use a single soft processor.
However, a few designers tile as many soft cores onto an FPGA as will fit.
In those multi-core systems, rarely used resources can be shared between all the cores in a cluster, leading to Jan's Razor.
While many people put exactly one soft microprocessor on a FPGA, a sufficiently large FPGA can hold two or more soft microprocessors,
resulting in a multi-core processor.
The number of soft processors on a single FPGA is only limited by the size of the FPGA.
Some people have put dozens or hundreds of soft microprocessors on a single FPGA.

Core comparison

Processor	Developer	Open Source	Bus Support	Notes	Project Home
TSK3000A	Altium	Royalty-Free	Wishbone Wishbone (computer bus) The Wishbone Bus is an open source hardware computer bus intended to let the parts of an integrated circuit communicate with each other. The aim is to allow the connection of differing cores to each other inside of a chip...	32-bit R3000 R3000 The R3000 is a microprocessor chip set developed by MIPS Computer Systems that implemented the MIPS I instruction set architecture . Introduced in June 1988, it was the second MIPS implementation, succeeding the R2000 as the flagship MIPS microprocessor... style RISC Modified Harvard Architecture CPU	Embedded Design on Altium Wiki
TSK51/52	Altium	Royalty-Free	Wishbone Wishbone (computer bus) The Wishbone Bus is an open source hardware computer bus intended to let the parts of an integrated circuit communicate with each other. The aim is to allow the connection of differing cores to each other inside of a chip... / Intel 8051 Intel 8051 The Intel MCS-51 is a Harvard architecture, single chip microcontroller series which was developed by Intel in 1980 for use in embedded systems. Intel's original versions were popular in the 1980s and early 1990s. While Intel no longer manufactures the MCS-51, binary compatible derivatives remain...	8-bit Intel 8051 Intel 8051 The Intel MCS-51 is a Harvard architecture, single chip microcontroller series which was developed by Intel in 1980 for use in embedded systems. Intel's original versions were popular in the 1980s and early 1990s. While Intel no longer manufactures the MCS-51, binary compatible derivatives remain... instruction set compatible, lower clock cycle alternative	Embedded Design on Altium Wiki
OpenSPARC T1 OpenSPARC OpenSPARC is an open-source hardware project started in December 2005. The initial contribution to the project was Sun Microsystems' register-transfer level Verilog code for a full 64-bit, 32-thread microprocessor, the UltraSPARC T1 processor. On 21 March 2006, Sun released the source code to the...	Sun Sun Microsystems Sun Microsystems, Inc. was a company that sold :computers, computer components, :computer software, and :information technology services. Sun was founded on February 24, 1982...			64-bit	OpenSPARC.net
MicroBlaze MicroBlaze The MicroBlaze is a soft processor core designed for Xilinx FPGAs from Xilinx. As a soft-core processor, MicroBlaze is implemented entirely in the general-purpose memory and logic fabric of Xilinx FPGAs.-Overview:...	Xilinx Xilinx Xilinx, Inc. is a supplier of programmable logic devices. It is known for inventing the field programmable gate array and as the first semiconductor company with a fabless manufacturing model....		PLB, OPB, FSL, LMB, AXI4		Xilinx MicroBlaze
PicoBlaze Picoblaze PicoBlaze is the designation of a series of three free soft processor cores from Xilinx for use in their FPGA and CPLD products. They are based on a RISC architecture of 8 bits and can reach speeds up to 100 MIPS on the Virtex 4 FPGA's family. The processors have an 8-bit address and data port for...	Xilinx Xilinx Xilinx, Inc. is a supplier of programmable logic devices. It is known for inventing the field programmable gate array and as the first semiconductor company with a fabless manufacturing model....				Xilinx PicoBlaze
Nios, Nios II Nios II Nios II is a 32-bit embedded-processor architecture designed specifically for the Altera family of FPGAs. Nios II incorporates many enhancements over the original Nios architecture, making it more suitable for a wider range of embedded computing applications, from DSP to system-control.Nios II is...	Altera Altera Altera Corporation is a Silicon Valley manufacturer of PLDs . The company offered its first programmable logic device in 1984. PLDs can be reprogrammed during the design cycle as well as in the field to perform multiple functions, and they support a fairly fast design process...		Avalon		Altera Nios II
Cortex-M1	ARM ARM Holdings ARM Holdings plc is a British multinational semiconductor and software company headquartered in Cambridge. Its largest business is in processors, although it also designs, licenses and sells software development tools under the RealView and KEIL brands, systems and platforms, system-on-a-chip...				http://www.arm.com/products/CPUs/ARM_Cortex-M1.html
eSi-RISC ESi-RISC eSi-RISC is a configurable CPU architecture from EnSilica. It is currently available in three different implementations: the eSi-1600, eSi-3200 and eSi-3250. The eSi-1600 features a 16-bit data-path, while the eSi-3200 and eSi-3250 feature 32-bit data-paths...	EnSilica		AMBA AXI, AHB and APB	Configurable as 16 or 32-bit. Supports ASIC and FPGA.	EnSilica eSi-RISC
LatticeMico32 LatticeMico32 LatticeMico32 is a 32-bit microprocessor soft core from Lattice Semiconductor optimized for field-programmable gate arrays . It uses a Harvard architecture, which means the instruction and data buses are separate. Bus arbitration logic can be used to combine the two buses, if desired.LatticeMico32...	Lattice Lattice Semiconductor Lattice Semiconductor Corporation is a United States based manufacturer of high-performance programmable logic devices . Founded in 1983, the company employs about 700 people and has annual revenues of around $300 million, with Darin Billerbeck as the chief executive officer...		Wishbone Wishbone (computer bus) The Wishbone Bus is an open source hardware computer bus intended to let the parts of an integrated circuit communicate with each other. The aim is to allow the connection of differing cores to each other inside of a chip...		LatticeMico32
LEON2(-FT) LEON LEON is a 32-bit CPU microprocessor core, based on the SPARC-V8 RISC architecture and instruction set. It was originally designed by the European Space Research and Technology Centre , part of the European Space Agency , and after that by Gaisler Research. It is described in synthesizable VHDL...	ESA European Space Agency The European Space Agency , established in 1975, is an intergovernmental organisation dedicated to the exploration of space, currently with 18 member states...		AMBA2	SPARC V8	ESA
LEON3/4 LEON LEON is a 32-bit CPU microprocessor core, based on the SPARC-V8 RISC architecture and instruction set. It was originally designed by the European Space Research and Technology Centre , part of the European Space Agency , and after that by Gaisler Research. It is described in synthesizable VHDL...	Aeroflex Gaisler		AMBA2	SPARC V8	Aeroflex Gaisler
Navré	Sébastien Bourdeauducq		Direct SRAM	Atmel AVR Atmel AVR The AVR is a modified Harvard architecture 8-bit RISC single chip microcontroller which was developed by Atmel in 1996. The AVR was one of the first microcontroller families to use on-chip flash memory for program storage, as opposed to one-time programmable ROM, EPROM, or EEPROM used by other... compatible 8-bit RISC	Project page at Opencores
OpenRISC OpenRISC OpenRISC is the original flagship project of the OpenCores community. This project aims to develop a series of general purpose open source RISC CPU architectures...	OpenCores OpenCores OpenCores is the world's largest open source hardware community developing digital open source hardware through electronic design automation, with a similar ethos to the free software movement. OpenCores hopes to eliminate redundant design work and slash development costs. A number of companies...		Wishbone Wishbone (computer bus) The Wishbone Bus is an open source hardware computer bus intended to let the parts of an integrated circuit communicate with each other. The aim is to allow the connection of differing cores to each other inside of a chip...	32-bit; Done in ASIC, Actel, Altera, Xilinx FPGA	OR1K
pAVR	Doru Cuturela			Atmel AVR Atmel AVR The AVR is a modified Harvard architecture 8-bit RISC single chip microcontroller which was developed by Atmel in 1996. The AVR was one of the first microcontroller families to use on-chip flash memory for program storage, as opposed to one-time programmable ROM, EPROM, or EEPROM used by other... compatible 8-bit RISC	Project page at Opencores
AEMB	Shawn Tan		Wishbone Wishbone (computer bus) The Wishbone Bus is an open source hardware computer bus intended to let the parts of an integrated circuit communicate with each other. The aim is to allow the connection of differing cores to each other inside of a chip...	MicroBlaze EDK 3.2 compatible Verilog core	AEMB
OpenFire	Virginia Tech CCM Lab		OPB, FSL	Binary compatible with the MicroBlaze	http://www.ccm.ece.vt.edu/~scraven/openfire.html
SecretBlaze	Lyonel Barthe		Wishbone Wishbone (computer bus) The Wishbone Bus is an open source hardware computer bus intended to let the parts of an integrated circuit communicate with each other. The aim is to allow the connection of differing cores to each other inside of a chip...	MicroBlaze ISA, VHDL	SecretBlaze
PacoBlaze	Pablo Bleyer			Compatible with the PicoBlaze processors	PacoBlaze
CPU86	HT-Lab			8088 compatible CPU in VHDL	cpu86
xr16	Jan Gray		XSOC abstract bus	16-bit RISC CPU + SoC featured in Circuit Cellar Magazine #116-118	XSOC/xr16
JOP Java optimized processor Java Optimized Processor is a Java processor, an implementation of Java Virtual Machine in hardware.JOP is free hardware under the GNU General Public License, ....	Martin Schoeberl		SimpCon / Wishbone Wishbone (computer bus) The Wishbone Bus is an open source hardware computer bus intended to let the parts of an integrated circuit communicate with each other. The aim is to allow the connection of differing cores to each other inside of a chip... (extension)	Stack oriented, hard real-time support, executes Java bytecode Java bytecode Java bytecode is the form of instructions that the Java virtual machine executes. Each bytecode opcode is one byte in length, although some require parameters, resulting in some multi-byte instructions. Not all of the possible 256 opcodes are used. 51 are reserved for future use... directly	Jop
ERIC5	Entner Electronics			9-bit RISC, very small size, C-programmable	ERIC5
YASEP	Yann Guidon	AGPLv3	Direct SRAM	16 or 32 bits, VHDL & JavaScript, not ready, sort of anti-F-CPU	yasep.org (Firefox required)
Zet	Zeus Gómez Marmolejo		Wishbone Wishbone (computer bus) The Wishbone Bus is an open source hardware computer bus intended to let the parts of an integrated circuit communicate with each other. The aim is to allow the connection of differing cores to each other inside of a chip...	x86 PC clone	Zet
ZPU	Zylin AS		Wishbone Wishbone (computer bus) The Wishbone Bus is an open source hardware computer bus intended to let the parts of an integrated circuit communicate with each other. The aim is to allow the connection of differing cores to each other inside of a chip...	Stack based CPU, configurable 16/32 bit datapath, eCos ECos eCos is an open source, royalty-free, real-time operating system intended for embedded systems and applications which need only one process with multiple threads. It is designed to be customizable to precise application requirements of run-time performance and hardware needs... support	Zylin CPU

External links

Soft CPU Cores for FPGA
Detailed Comparison of 12 Soft Microprocessors - broken link?
FPGA CPU News
Freedom CPU website (site damaged after the server was compromised)
Microprocessor cores on Opencores.org (Expand the "Processor" tab)
NikTech 32 bit RISC Microprocessor MANIK.

The source of this article is wikipedia, the free encyclopedia. The text of this article is licensed under the GFDL.

Core comparison

See also

External links