MicroBlaze
Encyclopedia
The MicroBlaze is a soft processor
core designed for Xilinx FPGA
s from Xilinx
. As a soft-core processor, MicroBlaze is implemented entirely in the general-purpose memory and logic fabric of Xilinx FPGAs.
-based DLX
architecture described in a popular computer architecture book by Patterson and Hennessy
. With few exceptions, the MicroBlaze can issue a new instruction every cycle, maintaining single-cycle throughput under most circumstances.
The MicroBlaze has a versatile interconnect system to support a variety of embedded applications. MicroBlaze's primary I/O bus, the CoreConnect
PLB bus, is a traditional system-memory mapped transaction bus with master/slave capability. A newer version of the MicroBlaze, supported in both Spartan-6 and Virtex-6 implementations, as well as the 7-Series, supports the AXI specification. The majority of vendor-supplied and third-party IP interface to PLB directly (or through an PLB to OPB bus bridge.) For access to local-memory (FPGA BRAM), MicroBlaze uses a dedicated LMB bus, which reduces loading on the other buses. User-defined coprocessors are supported through a dedicated FIFO-style connection called FSL (Fast Simplex Link). The coprocessor(s) interface can accelerate computationally intensive algorithms by offloading parts or the entirety of the computation to a user-designed hardware module.
Many aspects of the MicroBlaze can be user configured: cache size, pipeline depth (3-stage or 5-stage), embedded peripherals, memory management unit
, and bus-interfaces can be customized. The area-optimized version of MicroBlaze, which uses a 3-stage pipeline, sacrifices clock-frequency for reduced logic-area. The performance-optimized version expands the execution-pipeline to 5-stages, allowing top speeds of 210 MHz (*on Virtex-5 FPGA
family.) Also, key processor instructions
which are rarely used but more expensive to implement in hardware can be selectively added/removed
(i.e. multiply, divide, and floating-point ops.) This customization enables a developer to make the appropriate design tradeoffs for a specific set of host hardware and application software requirements.
With the memory management unit
, MicroBlaze is capable of hosting operating systems requiring hardware-based paging and protection, such as the Linux kernel
. Otherwise it is limited to operating systems with a simplified protection and virtual memory-model: e.g. FreeRTOS
or Linux without MMU support. MicroBlaze's overall throughput is substantially less than a comparable hardened CPU-core (such as the PowerPC440 in the Virtex-5.)
, the project manager consists of two separate environments: XPS and SDK.
Designers use XPS (Xilinx Platform Studio) to configure and build the hardware specification of their embedded system (processor core, memory-controller, I/O peripherals, etc.) The XPS converts the designer's platform specification into a synthesizeable RTL
description (Verilog
or VHDL), and writes a set of scripts to automate the implementation of the embedded system (from RTL to the bitstream-file.) For the MicroBlaze core, the EDK normally generates an encrypted (non human-readable) netlist, but the processor description (written in VHDL) can be purchased from Xilinx.
The SDK handles the software that will execute on the embedded system. Powered by the GNU toolchain
(GNU Compiler Collection
, GNU Debugger
), the SDK enables programmers to write, compile, and debug C/C++ applications for their embedded system. Xilinx includes a cycle-accurate instruction set simulator (ISS), giving programmers the choice of testing their software in simulation, or using a suitable FPGA-board to download and execute on the actual system.
Purchasers of EDK or ISE Design Suite Embedded Edition(IDS) are granted a perpetual license to use MicroBlaze in Xilinx FPGAs with no recurring royalties. The license does not grant the right to use MicroBlaze outside of Xilinx's devices, which must be negotiated directly with Xilinx.
Alternative compilers and development tools have been made available from Altium but an EDK installation and license is still required.
In May, 2009, Edgar E. Iglesias contributed a MicroBlaze guest port for QEMU.
As of September 2009, MicroBlaze GNU tools support is also being contributed to the Free Software Foundation's mainline repositories. Support for MicroBlaze is included in GCC releases starting with version 4.6
.
Soft microprocessor
A soft microprocessor is a microprocessor core that can be wholly implemented using logic synthesis...
core designed for Xilinx FPGA
Field-programmable gate array
A field-programmable gate array is an integrated circuit designed to be configured by the customer or designer after manufacturing—hence "field-programmable"...
s from Xilinx
Xilinx
Xilinx, Inc. is a supplier of programmable logic devices. It is known for inventing the field programmable gate array and as the first semiconductor company with a fabless manufacturing model....
. As a soft-core processor, MicroBlaze is implemented entirely in the general-purpose memory and logic fabric of Xilinx FPGAs.
Overview
In terms of its instruction-set architecture, MicroBlaze is very similar to the RISCReduced instruction set computer
Reduced instruction set computing, or RISC , is a CPU design strategy based on the insight that simplified instructions can provide higher performance if this simplicity enables much faster execution of each instruction. A computer based on this strategy is a reduced instruction set computer...
-based DLX
DLX
The DLX is a RISC processor architecture designed by John L. Hennessy and David A. Patterson, the principal designers of the MIPS and the Berkeley RISC designs , the two benchmark examples of RISC design. The DLX is essentially a cleaned up and simplified MIPS, with a simple 32-bit load/store...
architecture described in a popular computer architecture book by Patterson and Hennessy
John L. Hennessy
John LeRoy Hennessy is an American computer scientist and academician. Hennessy is one of the founders of MIPS Computer Systems Inc. and is the 10th President of Stanford University.-Background:...
. With few exceptions, the MicroBlaze can issue a new instruction every cycle, maintaining single-cycle throughput under most circumstances.
The MicroBlaze has a versatile interconnect system to support a variety of embedded applications. MicroBlaze's primary I/O bus, the CoreConnect
CoreConnect
CoreConnect is a microprocessor bus-architecture from IBM for system-on-a-chip designs. Designed to ease the integration and reuse of processor, system, and peripheral cores within standard and custom SoC designs. As a standard SoC design point, it serves as the foundation of IBM or non-IBM devices...
PLB bus, is a traditional system-memory mapped transaction bus with master/slave capability. A newer version of the MicroBlaze, supported in both Spartan-6 and Virtex-6 implementations, as well as the 7-Series, supports the AXI specification. The majority of vendor-supplied and third-party IP interface to PLB directly (or through an PLB to OPB bus bridge.) For access to local-memory (FPGA BRAM), MicroBlaze uses a dedicated LMB bus, which reduces loading on the other buses. User-defined coprocessors are supported through a dedicated FIFO-style connection called FSL (Fast Simplex Link). The coprocessor(s) interface can accelerate computationally intensive algorithms by offloading parts or the entirety of the computation to a user-designed hardware module.
Many aspects of the MicroBlaze can be user configured: cache size, pipeline depth (3-stage or 5-stage), embedded peripherals, memory management unit
Memory management unit
A memory management unit , sometimes called paged memory management unit , is a computer hardware component responsible for handling accesses to memory requested by the CPU...
, and bus-interfaces can be customized. The area-optimized version of MicroBlaze, which uses a 3-stage pipeline, sacrifices clock-frequency for reduced logic-area. The performance-optimized version expands the execution-pipeline to 5-stages, allowing top speeds of 210 MHz (*on Virtex-5 FPGA
Field-programmable gate array
A field-programmable gate array is an integrated circuit designed to be configured by the customer or designer after manufacturing—hence "field-programmable"...
family.) Also, key processor instructions
Application-specific instruction-set processor
An application-specific instruction-set processor is a component used in system-on-a-chip design. The instruction set of an ASIP is tailored to benefit a specific application. This specialization of the core provides a tradeoff between the flexibility of a general purpose CPU and the performance...
which are rarely used but more expensive to implement in hardware can be selectively added/removed
Application-specific instruction-set processor
An application-specific instruction-set processor is a component used in system-on-a-chip design. The instruction set of an ASIP is tailored to benefit a specific application. This specialization of the core provides a tradeoff between the flexibility of a general purpose CPU and the performance...
(i.e. multiply, divide, and floating-point ops.) This customization enables a developer to make the appropriate design tradeoffs for a specific set of host hardware and application software requirements.
With the memory management unit
Memory management unit
A memory management unit , sometimes called paged memory management unit , is a computer hardware component responsible for handling accesses to memory requested by the CPU...
, MicroBlaze is capable of hosting operating systems requiring hardware-based paging and protection, such as the Linux kernel
Linux kernel
The Linux kernel is an operating system kernel used by the Linux family of Unix-like operating systems. It is one of the most prominent examples of free and open source software....
. Otherwise it is limited to operating systems with a simplified protection and virtual memory-model: e.g. FreeRTOS
FreeRTOS
FreeRTOS is a real-time operating system for embedded devices, being ported to several microcontrollers. It is distributed under the GPL with an optional exception...
or Linux without MMU support. MicroBlaze's overall throughput is substantially less than a comparable hardened CPU-core (such as the PowerPC440 in the Virtex-5.)
EDK
Xilinx's EDK (Embedded Development Kit) is the development package for building MicroBlaze (and PowerPC) embedded processor systems in Xilinx FPGAs. Hosted in the Eclipse IDEEclipse (software)
Eclipse is a multi-language software development environment comprising an integrated development environment and an extensible plug-in system...
, the project manager consists of two separate environments: XPS and SDK.
Designers use XPS (Xilinx Platform Studio) to configure and build the hardware specification of their embedded system (processor core, memory-controller, I/O peripherals, etc.) The XPS converts the designer's platform specification into a synthesizeable RTL
Register transfer level
In integrated circuit design, register-transfer level is a level of abstraction used in describing the operation of a synchronous digital circuit...
description (Verilog
Verilog
In the semiconductor and electronic design industry, Verilog is a hardware description language used to model electronic systems. Verilog HDL, not to be confused with VHDL , is most commonly used in the design, verification, and implementation of digital logic chips at the register-transfer level...
or VHDL), and writes a set of scripts to automate the implementation of the embedded system (from RTL to the bitstream-file.) For the MicroBlaze core, the EDK normally generates an encrypted (non human-readable) netlist, but the processor description (written in VHDL) can be purchased from Xilinx.
The SDK handles the software that will execute on the embedded system. Powered by the GNU toolchain
GNU toolchain
The GNU toolchain is a blanket term for a collection of programming tools produced by the GNU Project. These tools form a toolchain used for developing applications and operating systems....
(GNU Compiler Collection
GNU Compiler Collection
The GNU Compiler Collection is a compiler system produced by the GNU Project supporting various programming languages. GCC is a key component of the GNU toolchain...
, GNU Debugger
GNU Debugger
The GNU Debugger, usually called just GDB and named gdb as an executable file, is the standard debugger for the GNU software system. It is a portable debugger that runs on many Unix-like systems and works for many programming languages, including Ada, C, C++, Objective-C, Free Pascal, Fortran, Java...
), the SDK enables programmers to write, compile, and debug C/C++ applications for their embedded system. Xilinx includes a cycle-accurate instruction set simulator (ISS), giving programmers the choice of testing their software in simulation, or using a suitable FPGA-board to download and execute on the actual system.
Purchasers of EDK or ISE Design Suite Embedded Edition(IDS) are granted a perpetual license to use MicroBlaze in Xilinx FPGAs with no recurring royalties. The license does not grant the right to use MicroBlaze outside of Xilinx's devices, which must be negotiated directly with Xilinx.
Alternative compilers and development tools have been made available from Altium but an EDK installation and license is still required.
Open Source
In June, 2009, MicroBlaze became the first soft-CPU architecture to be merged into the mainline Linux Kernel Source tree. This work was performed by Michal Simek and supported by PetaLogix and Xilinx.In May, 2009, Edgar E. Iglesias contributed a MicroBlaze guest port for QEMU.
As of September 2009, MicroBlaze GNU tools support is also being contributed to the Free Software Foundation's mainline repositories. Support for MicroBlaze is included in GCC releases starting with version 4.6
.
Clones
- aeMB, implemented in VerilogVerilogIn the semiconductor and electronic design industry, Verilog is a hardware description language used to model electronic systems. Verilog HDL, not to be confused with VHDL , is most commonly used in the design, verification, and implementation of digital logic chips at the register-transfer level...
, LGPL license - MB-Lite, implemented in VHDL, LGPL license
- myBlaze, implemented in MyHDLMyHDLMyHDL is a Python based hardware description language .Features of MyHDL include:* The ability to generate VHDL and Verilog code from a MyHDL design....
, LGPL license - SecretBlaze, implemented in VHDL, GPL license
Other soft processors
- TSK3000
- Xtensa
See also
- OpenCoresOpenCoresOpenCores is the world's largest open source hardware community developing digital open source hardware through electronic design automation, with a similar ethos to the free software movement. OpenCores hopes to eliminate redundant design work and slash development costs. A number of companies...
- a home for many open sourceOpen sourceThe term open source describes practices in production and development that promote access to the end product's source materials. Some consider open source a philosophy, others consider it a pragmatic methodology...
soft processor projects - PicoBlazePicoblazePicoBlaze is the designation of a series of three free soft processor cores from Xilinx for use in their FPGA and CPLD products. They are based on a RISC architecture of 8 bits and can reach speeds up to 100 MIPS on the Virtex 4 FPGA's family. The processors have an 8-bit address and data port for...
External links
- MicroBlaze on Xilinx website
- PetaLogix - MicroBlaze kernel maintainers and commercial services (PetaLinux)
- uCLinux - uClinux-dist for Microblaze, kernel 2.6.30
- MicroBlaze Embedded Linux support from LynuxWorks (BlueCat Linux)
- Linux and U-BOOT for Microblaze CPU - Michal Simek - maintainer
- MicroBlaze-Based Introduction To Computer Architecture and Assembly Language (UARK)
- MicroBlaze managed forum