Media Independent Interface

The Media Independent Interface (MII) was originally defined as a standard interface used to connect a Fast Ethernet

Fast Ethernet

In computer networking, Fast Ethernet is a collective term for a number of Ethernet standards that carry traffic at the nominal rate of 100 Mbit/s, against the original Ethernet speed of 10 Mbit/s. Of the fast Ethernet standards 100BASE-TX is by far the most common and is supported by the...

(i.e. ) MAC

Media Access Control

The media access control data communication protocol sub-layer, also known as the medium access control, is a sublayer of the data link layer specified in the seven-layer OSI model , and in the four-layer TCP/IP model...

-block to a PHY chip.

The MII design has been extended to support reduced signals and increases speeds. Current variants are Reduced Media Independent Interface, Gigabit Media Independent Interface, Reduced Gigabit Media Independent Interface, Serial Gigabit Media Independent Interface and 10 Gigabit Media Independent Interface.

The equivalent of MII for 10 megabit Ethernet is the Attachment Unit Interface

Attachment Unit Interface

An Attachment Unit Interface is a 15 pin connection that provides a path between a node's Ethernet interface and the Medium Attachment Unit , sometimes known as a transceiver. It is the part of the IEEE Ethernet standard located between the Media Access Control , and the MAU...

Being media independent means that different types of PHY devices for connecting to different media (i.e. Twisted pair copper, fiber optic, etc.) can be used without redesigning or replacing the MAC

Media Access Control

hardware. The MII bus (standardized by IEEE 802.3u) connects different types of PHYs (Physical Transceivers) to Media Access Controllers (MAC

Media Access Control

). Thus any MAC may be used with any PHY, independent of the network signal transmission media. The MII bus transfers data using 4-bit words (nibble

Nibble

In computing, a nibble is a four-bit aggregation, or half an octet...

) in each direction (4 transmit data bits, 4 receive data bits). The data is clocked at 25 MHz to achieve 100 Mbit/s speed.

The MII can be used to connect a MAC to an external PHY using a pluggable connector (shown in the figure (extreme right)), or direct to a PHY chip which is on the same printed circuit board. On a PC the CNR connector

Communications and Networking Riser

Communications and Networking Riser is a slot found on certain PC motherboards and used for specialized networking, audio, and telephony equipment. A motherboard manufacturer can choose to provide audio, networking, or modem functionality in any combination on a CNR card...

Type B carries MII bus interface signals.

The MDIO Serial Management Interface (SMI) (see MDIO) is used to transfer management information between MAC

Media Access Control

and PHY.

The standard MII features a small set of registers:

Basic Mode Configuration (#0)
Status Word (#1)
PHY Identification (#2, #3)
Ability Advertisement (#4)
Link Partner Ability (#5)
Auto Negotiation Expansion (#6)

The MII Status Word is the most useful datum, since it may be used to detect whether an Ethernet NIC is connected to a network. It contains a bitmask with the following meaning:

0x8000 Capable of 100baseT4
0x7800 Capable of 10/100 HD/FD (most common)
0x0040 Preamble suppression permitted
0x0020 Autonegotiation complete
0x0010 Remote fault
0x0008 Capable of Autonegotiation
0x0004 Link established
0x0002 Jabber detected
0x0001 Extended MII register exist.

A more detailed reference on registers exported by MII-compatible PHY's
can be found looking at the Linux MII interface definition (include/linux/mii.h)
http://lxr.linux.no/source/include/linux/mii.h

In operation of data transmission, the transmit enable signal (TXEN) is asserted Active to indicate the start of a Ethernet frame, and is held active until the frame's transmission is completed. Simultaneously, the transmit clock signal (TXCLK) is set to Active for every new group of data bits (TXD0-TXD3). At 2.5 MHz for 10 Mbit/s mode and 25 MHz for 100 Mbit/s mode.

During reception the receive data valid signal (RXDV) goes active when the frame starts, and is held active throughout the frame duration. The clock signal (RXCLK) goes active for every new group of receive data bits (RXD0-RXD3). For the shortest possible frame size of 64 bytes, this means ~130 clocks. Any frame transferred begins with sync bits before the data payload. At powerup the PHY usually adapts to whatever it's connected to (Auto-negotiation) unless you alter settings via the MDIO interface.

Reduced Media Independent Interface

Reduced Media Independent Interface (RMII) is a standard that addresses the connection of Ethernet

Ethernet

Ethernet is a family of computer networking technologies for local area networks commercially introduced in 1980. Standardized in IEEE 802.3, Ethernet has largely replaced competing wired LAN technologies....

physical layer transceivers (PHY) to Ethernet switches or the MAC portion of an end-device's Ethernet interface. It reduces the number of signals/pins required for connecting to the PHY from 16 (for an MII

Media Independent Interface

The Media Independent Interface was originally defined as a standard interface used to connect a Fast Ethernet MAC-block to a PHY chip.The MII design has been extended to support reduced signals and increases speeds...

-compliant interface) to between 6 and 10. RMII is capable of supporting 10 and 100 Mbit/s; gigabit interfaces need a wider interface.

An Ethernet interface normally consists of 4 major parts: The MAC

Media Access Control

(Media Access Controller), the PHY (PHYsical Interface or transceiver), the magnetics, and the connector. Connectors with integrated magnetics are available. The MAC handles the high level portions of the Ethernet protocol (framing, error detection, when to transmit, etc.) and the PHY handles the low level logic (4B/5B encoding/decoding, SERDES

SerDes

A Serializer/Deserializer is a pair of functional blocks commonly used in high speed communications to compensate for limited input/output. These blocks convert data between serial data and parallel interfaces in each direction...

(serialization/deserialization), and NRZI encoding/decoding) and analog portions. RMII is one of the possible interfaces between the MAC and PHY; others include MII and SNI, with additional wider interfaces (including XAUI

XAUI

XAUI is a standard for extending the XGMII between the MAC and PHY layer of 10 Gigabit Ethernet . XAUI is pronounced "zowie", a concatenation of the Roman numeral X, meaning ten, and the initials of "Attachment Unit Interface"...

, GBIC, SFP

SFP transceiver

The small form-factor pluggable or Mini-GBIC is a compact, hot-pluggable transceiver used for both telecommunication and data communications applications. It interfaces a network device mother board to a fiber optic or copper networking cable...

, SFF, XFP

XFP transceiver

The XFP is a standard for transceivers for high-speed computer network and telecommunication links that use optical fiber. It was defined by an industry group in 2002, along with its interface to other electrical components which is called XFI.-Description:XFP modules are hot-swappable and...

, and XFI) for gigabit and faster Ethernet links.

One or more MAC interfaces may be on the same chip and in some cases the chip may have many other functions. One or more PHY interfaces may be on the same chip, particularly in Ethernet switches. Some MAC and PHY ICs support both MII and RMII. Usually, the MAC and PHY are on the same board for 10/100 Ethernet though for gigabit and higher pluggable PHY modules may be used to allow the use of different media including twisted pair and optical fiber. Older coaxial Ethernet interfaces sometimes used an AUI

Attachment Unit Interface

interface between the MAC and transceiver which was often an external box (thicknet required an external transceiver).

By comparison, the MII interface requires two additional data lines in each direction, RX_DV and CRS are separate rather than multiplexed, a separate TX_CLK and RX_CLK are used instead of a shared reference clock, and a collision signal is added for a total of 7 additional lines.
The added pin count is more of a burden on microcontroller

Microcontroller

A microcontroller is a small computer on a single integrated circuit containing a processor core, memory, and programmable input/output peripherals. Program memory in the form of NOR flash or OTP ROM is also often included on chip, as well as a typically small amount of RAM...

s with built in MAC, FPGA

Field-programmable gate array

A field-programmable gate array is an integrated circuit designed to be configured by the customer or designer after manufacturing—hence "field-programmable"...

's, multitport switches or repeaters, and PC motherboard chipsets than it is for a separate single port Ethernet MAC which partially explains why the older MII standard was more wasteful of pins.

Signals

TXD0 Transmit data bit 0 (MAC to PHY) (transmitted first)
TXD1 Transmit data bit 1 (MAC to PHY)
TX_EN When high, clock data on TXD0 and TXD1 to the transmitter (MAC to PHY)
RXD0 Receive data bit 0 (PHY to MAC) (received first)
RXD1 Receive data bit 1 (PHY to MAC)
CRS_DV, Carrier Sense (CRS)/RX_Data Valid(RX_DV) multiplexed on alternate clock cycles. In 10 Mbit/s mode, it alternates every 10 clock cycles. (PHY to MAC)
RX_ER Receive Error (optional on switches) (PHY to MAC)
REF_CLK Continuous 50 MHz Reference Clock (may be shared among interfaces). Reference clock may be an input on both devices or may be driven from MAC to PHY.
MDIO Management data I/O line (IIC/SMBus/TWI compatible) (bidirectional, open drain)
MDC Management data clock line (bidirectional but MAC to PHY in practice (though perhaps the PHY can pull down MDC to slow transfer), open drain). MDC and MDIO can in some cases be shared among multiple PHYs and with other devices.

On multiport devices, MDIO, MDC, and REF_CLK may be shared leaving 6 or 7 pins per port.

RMII requires a clock where MII requires a clock and data is clocked out two bits at a time vs 4 bits at a time for MII or 1 bit at a time for SNI (10 Mbit/s only). Data is sampled on the rising edge only. Ie it's not double pumped.

Limitations

In mode, TXD0/TXD1/RXD0/RXD1 are sampled on every tenth clock cycle. The standard does a poor job of explaining the timing of signals in 10 Mbit/s mode. Apparently data on signal lines is supposed to remain valid for 10 clock cycles so it can be sampled on any clock edge during that interval. TX_EN probably remains asserted for the duration of the packet. It appears that 10 Mbit/s mode can be implemented by inserting a divide by 10 prescaler with pulse gate or separate clock enable line. It does not appear that the prescaler has to be reset to synchronize it with any particular event; instead the two prescalers (MAC and PHY) operate asynchronously with respect to each other.

There is no signal which defines whether the interface is in 10 or 100 Mbit/s mode but obviously both the MAC and the PHY need to agree. This is presumably handled by the MDIO/MDC interface though things might get interesting if the PHY and switch renegotiate the link speed at an unexpected time (perhaps after a cable was disconnected and reconnected). Future versions of the RMII standard might specify a way to transmit data over TXD0/TXD1/RXD0/RXD1 pins while TX_EN and CRS_DV are de-asserted.

The missing COL signal is derived from AND-ing together the TX_EN and the decoded CRS signal from the CRS_DV line in half duplex mode. The lack of the RX_ER signal which is not connected on some MACs (such as multiport switches) is dealt with by data replacement on some PHYs to invalidate the CRC

Cyclic redundancy check

A cyclic redundancy check is an error-detecting code commonly used in digital networks and storage devices to detect accidental changes to raw data...

.

RMII has no COL signal. Instead the COL signal is recreated by a logical AND operation of CRS and TX_EN. This change means there is a slight modification of the definition of CRS. On MII, CRS is asserted for both Rx and Tx frames. But on RMII the CRS signal is only asserted for Rx frames. This has a few consequences: The two error conditions "no carrier" and "lost carrier" cannot be detected on RMII. And furthermore, it is difficult or impossible to support shared media such as Thinnet with RMII.

Signal levels

TTL signal levels are used for or logic. Input high threshold is and low is . The specification specifies that inputs should be tolerant, however, some popular chips with RMII interfaces are not tolerant. Given trends in the semiconductor industry and the fact that both ICs are usually on the same board, lack of tolerance is probably very common, and chips that actually drive are probably even rarer. tolerance is probably found primarily on older MII only devices. On the other hand, newer devices may support and logic. National.com doesn't make tolerant RMII PHYs. National DP83848: no . SMSC LAN8187: to , not tolerant. Intel LXT9781/LXT9761 8/6 port PHY: tolerant. Atmel AT91SAM7XC256 microcontroller: tolerant, AMD 79C875 4 port PHY: tolerant, FPGAs sufficient to implement MAC are usually not tolerant.

The RMII signals are treated as lumped signals rather than transmission lines; no termination or controlled impedance is necessary; output drive (and thus slew rates) need to be as slow as possible (rise times from ) in order to permit this. Drivers should be able to drive of capacitance which allows for PCB traces up to . At least the standard says the signals need not be treated as transmission lines. However, at edge rates a trace longer than about (1ns/(5.9ns/m)*(3.7 m/0.0254 m)*(1/6)), transmission line effects could be a significant problem; at , traces can be longer. The IEEE version of the related MII standard specifies trace impedance. National recommends running traces with (adds to driver output impedance) series termination resistors for either MII or RMII mode to reduce reflections. National also suggests that traces be kept under long and matched within on length to minimize skew.

Since the RMII standard neglected to stipulate that TX_EN should only be sampled on alternate clock cycles, it is not symmetric with CRS_DV and two RMII PHY devices cannot be connected back to back to form a repeater; this is possible, however, with the National DP83848 which supplies the decoded RX_DV as a supplemental signal in RMII mode

Gigabit Media Independent Interface

Gigabit Media Independent Interface (GMII) is an interface between the Media Access Control

Media Access Control

(MAC) device and the physical layer (PHY

PHY

PHY is an abbreviation for the physical layer of the OSI model.An instantiation of PHY connects a link layer device to a physical medium such as an optical fiber or copper cable. A PHY device typically includes a Physical Coding Sublayer and a Physical Medium Dependent layer. The PCS encodes and...

). The interface defines speeds up to 1000 Mbit/s, implemented using an eight bit data interface clocked at 125 MHz, and is backwards compatible with the Media Independent Interface

Media Independent Interface

(MII) specification. It can also operate on fall-back speeds of 10/100 Mbit/s as per the MII specification.

Data on the interface is framed using the IEEE Ethernet

Ethernet

standard. As such it consists of a preamble, start of frame delimiter, Ethernet headers, protocol specific data and a cyclic redundancy check

Cyclic redundancy check

A cyclic redundancy check is an error-detecting code commonly used in digital networks and storage devices to detect accidental changes to raw data...

(CRC) checksum.

The GMII interface is defined in IEEE Standard 802.3, 2000 Edition
http://ieeexplore.ieee.org/xpl/standardstoc.jsp?isnumber=19017

Transmitter

GTXCLK - clock signal for gigabit TX.. signals (125 MHz)
TXCLK - clock signal for 10/100 Mbit signals
TXD[7..0] - data to be transmitted
TXEN - transmitter enable
TXER - transmitter error (used to corrupt a packet)

There are two clocks, depending on whether the PHY is operating at gigabit or 10/100 Mb speeds. For gigabit speeds, the GTXCLK is supplied to the PHY and the TXD, TXEN, TXER signals are synchronized to this. Otherwise for 10/100 Mb the TXCLK (supplied by PHY) is used for synchronizing those signals. This operates at either 25 MHz for 100 Mbit/s or 2.5 MHz for 10 Mbit/s connections. The receiver clock is much simpler, with only one clock, which is recovered from the incoming data. Hence the GTXCLK and RXCLK are not coherent.

Receiver

RXCLK - received clock signal
Clock signal
In electronics and especially synchronous digital circuits, a clock signal is a particular type of signal that oscillates between a high and a low state and is utilized like a metronome to coordinate actions of circuits...

(recovered from incoming received data)
RXD[7..0] - received data
RXDV - signifies data received is valid
RXER - signifies data received has errors
COL - Collision Detect (half-duplex connections only)
CS - Carrier Sense (half-duplex connections only)

Management

MDC - Management interface clock
MDIO
MDIO
Management Data Input/Output , or also Media Independent Interface Management , is a serial bus defined for the Ethernet family of IEEE 802.3 standards for Media Independent Interface, or MII....

- Management interface I/O bidirectional pin.

The management interface controls the behaviour of the PHY. There are 32 addresses, each containing 16 bits. The first 16 addresses have a defined usage (see "IEEE 802.3,2000-22.2.4 Management Functions"), while the others are device specific. These registers can be used to configure the device (say "only gigabit, full duplex", or "only full duplex") or can be used to determine the current operating mode.

Reduced Gigabit Media Independent Interface

Reduced Gigabit Media Independent Interface (RGMII) specifies a particular interface between an Ethernet

Ethernet

MAC

Media Access Control

and PHY.

RGMII uses half the number of data pins as used in the GMII interface. This reduction is achieved by clocking data on both the rising and falling edges of the clock in 1000 Mbit/s operation, and by eliminating non-essential signals (carrier-sense and collision-indication). Thus RGMII consists only of: RX_CTL, RXC, RXD[3:0], TX_CTL, TXC, TXD[3:0] (12 pins, as opposed to GMII's 24). Ie FrameStart-BitClock-Data.

Unlike GMII, the transmit clock signal is always provided by the MAC on the TXC line, rather than being provided by the PHY for 10/100 Mbit/s operation and by the MAC at 1000 Mbit/s.

RGMII supports Ethernet speeds of:

[Mbit/s]	[MHz Hertz The hertz is the SI unit of frequency defined as the number of cycles per second of a periodic phenomenon. One of its most common uses is the description of the sine wave, particularly those used in radio and audio applications.... ]	Bits/Clockcycle
10	2.5	4
100	25	4
1000	125	8

Serial Gigabit Media Independent Interface

The Serial Gigabit Media Independent Interface (SGMII) is a variant of MII

Media Independent Interface

, a standard interface used to connect an Ethernet

Ethernet

MAC-block to a PHY

PHY

. It is used for Gigabit Ethernet

Gigabit Ethernet

Gigabit Ethernet is a term describing various technologies for transmitting Ethernet frames at a rate of a gigabit per second , as defined by the IEEE 802.3-2008 standard. It came into use beginning in 1999, gradually supplanting Fast Ethernet in wired local networks where it performed...

but can also carry 10/100 MBit Ethernet.

It uses differential pairs at 625 MHz clock frequency DDR for TX and RX data and TX and RX clocks.
It differs from GMII by its low-power and low pin count serial 8B/10B coded interface (commonly referred to as a SerDes

SerDes

). Transmit and receive path each use one differential pair for data and another differential pair for clock. The TX/RX clocks must be generated on device output but are optional on device input (Clock recovery

Clock recovery

Some digital data streams, especially high-speed serial data streams are sent without an accompanying clock signal. The receiver generates a clock from an approximate frequency reference, and then phase-aligns to the transitions in the data stream with a phase-locked loop...

may be used alternatively). 10/100 MBit Ethernet is carried by duplicating data words 100/10 times each, so the clock is always at 625 MHz.

10 Gigabit Media Independent Interface

10 Gigabit Media Independent Interface (XGMII) is a standard defined in IEEE 802.3

IEEE 802.3

IEEE 802.3 is a working group and a collection of IEEE standards produced by the working group defining the physical layer and data link layer's media access control of wired Ethernet. This is generally a local area network technology with some wide area network applications...

for connecting full duplex 10 Gigabit Ethernet

10 Gigabit Ethernet

The 10 gigabit Ethernet computer networking standard was first published in 2002. It defines a version of Ethernet with a nominal data rate of 10 Gbit/s , ten times faster than gigabit Ethernet.10 gigabit Ethernet defines only full duplex point to point links which are generally connected by...

(10GbE) ports to each other and to other electronic

Electronics

Electronics is the branch of science, engineering and technology that deals with electrical circuits involving active electrical components such as vacuum tubes, transistors, diodes and integrated circuits, and associated passive interconnection technologies...

devices on a printed circuit board

Printed circuit board

A printed circuit board, or PCB, is used to mechanically support and electrically connect electronic components using conductive pathways, tracks or signal traces etched from copper sheets laminated onto a non-conductive substrate. It is also referred to as printed wiring board or etched wiring...

. It is composed from two 32-bits datapaths (Rx & Tx) and two 4-bits control flows (Rxc & Txc), operating at 156.25 MHz DDR

Double data rate

In computing, a computer bus operating with double data rate transfers data on both the rising and falling edges of the clock signal. This is also known as double pumped, dual-pumped, and double transition....

(312.5 MT/s).

Typically used for on-chip connections; in chip-to-chip usage mostly replaced by XAUI

XAUI

External links

national.com - RMII specification
national.com - AN-1405 DP83848 RMII
national.com - DP83848C PHY Data Sheet
hp.com - RGMIIv2_0_final_hp.pdf (RGMII 2002-04-01 Version 2.0)
[ftp://ftp-eng.cisco.com/smii/sgmii.pdf Serial-GMII Specification Revision 1.8 (ENG-46158)]
Serial-GMII Specification Revision 1.7 (ENG-46158)
CEVA implementation documentation
Altera 10Gb Ethernet IP with XGMII and XAUI interfaces

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