List of ARM microprocessor cores - AbsoluteAstronomy.com

__FORCETOC__

This is a sub-article to ARM architecture

ARM architecture

ARM is a 32-bit reduced instruction set computer instruction set architecture developed by ARM Holdings. It was named the Advanced RISC Machine, and before that, the Acorn RISC Machine. The ARM architecture is the most widely used 32-bit ISA in numbers produced...

ARM's microprocessor cores are listed here, sorted by generation release and name. ARM provides a summary of the numerous vendors who implement ARM cores in their design. KEIL

KEIL

Keil was founded in 1982 by Günter und Reinhard Keil, initially as a German GbR. In April 1985 the company was converted to Keil Elektronik GmbH to market add-on products for the development tools provided by many of the silicon vendors...

also provides a somewhat newer summary of vendors of ARM based processors. ARM further provides a chart displaying an overview of the ARM processor lineup with performance and functionality versus capabilities for the more recent ARM7, ARM9, ARM11, Cortex-M, Cortex-R and Cortex-A device families.

ARM microprocessor cores

ARM Family	ARM Architecture	ARM Core	Feature	Cache (I/D), MMU Memory management unit A memory management unit , sometimes called paged memory management unit , is a computer hardware component responsible for handling accesses to memory requested by the CPU...	Typical MIPS @ MHz
ARM1	ARMv1	ARM1	First implementation	None
ARM2	ARMv2	ARM2	ARMv2 added the MUL (multiply) instruction	None	4 MIPS @ 8 MHz 0.33 DMIPS/MHz
ARM2	ARMv2a	ARM250	Integrated MEMC (MMU), Graphics and IO processor. ARMv2a added the SWP and SWPB (swap) instructions.	None, MEMC1a	7 MIPS @ 12 MHz
ARM3	ARMv2a	ARM3	First integrated memory cache.	4 KB unified	12 MIPS @ 25 MHz 0.50 DMIPS/MHz
ARM6	ARMv3	ARM60	ARMv3 first to support 32-bit memory address space (previously 26-bit)	None	10 MIPS @ 12 MHz
		ARM600	As ARM60, cache and coprocessor bus (for FPA10 floating-point unit).	4 KB unified	28 MIPS @ 33 MHz
		ARM610	As ARM60, cache, no coprocessor bus.	4 KB unified	17 MIPS @ 20 MHz 0.65 DMIPS/MHz
ARM7	ARMv3	ARM700		8 KB Kilobyte The kilobyte is a multiple of the unit byte for digital information. Although the prefix kilo- means 1000, the term kilobyte and symbol KB have historically been used to refer to either 1024 bytes or 1000 bytes, dependent upon context, in the fields of computer science and information... unified	40 MHz
		ARM710	As ARM700, no coprocessor bus.	8 KB unified	40 MHz
		ARM710a	As ARM710	8 KB unified	40 MHz 0.68 DMIPS/MHz
ARM7TDMI ARM7TDMI ARM7 is a generation of ARM processor designs. This generation introduced the Thumb 16-bit instruction set providing improved code density compared to previous designs. The most widely used ARM7 designs implement the ARMv4T architecture, but some implement ARMv3 or ARMv5TEJ...	ARMv4T	ARM7TDMI(-S)	3-stage pipeline, Thumb	none	15 MIPS @ 16.8 MHz 63 DMIPS @ 70 MHz
		ARM710T	As ARM7TDMI, cache	8 KB unified, MMU	36 MIPS @ 40 MHz
		ARM720T	As ARM7TDMI, cache	8 KB unified, MMU with Fast Context Switch Extension	60 MIPS @ 59.8 MHz
		ARM740T	As ARM7TDMI, cache	MPU
ARM7EJ	ARMv5TEJ	ARM7EJ-S	5-stage pipeline, Thumb, Jazelle DBX, Enhanced DSP instructions	none
ARM8	ARMv4	ARM810	5-stage pipeline, static branch prediction, double-bandwidth memory	8 KB unified, MMU	84 MIPS @ 72 MHz 1.16 DMIPS/MHz
StrongARM StrongARM The StrongARM is a family of microprocessors that implemented the ARM V4 instruction set architecture . It was developed by Digital Equipment Corporation and later sold to Intel, who continued to manufacture it before replacing it with the XScale....	ARMv4	SA-1	5-stage pipeline	16 KB/8–16 KB, MMU	203–206 MHz 1.0 DMIPS/MHz
ARM9TDMI	ARMv4T	ARM9TDMI	5-stage pipeline, Thumb	none
		ARM920T	As ARM9TDMI, cache	16 KB/16 KB, MMU with FCSE (Fast Context Switch Extension)	200 MIPS @ 180 MHz
		ARM922T	As ARM9TDMI, caches	8 KB/8 KB, MMU
		ARM940T	As ARM9TDMI, caches	4 KB/4 KB, MPU
ARM9E ARM9E ARM9 is an ARM architecture 32-bit RISC CPU family. With this design generation, ARM moved from a von Neumann architecture to a Harvard architecture with separate instruction and data buses , significantly increasing its potential speed...	ARMv5TE	ARM946E-S	Thumb, Enhanced DSP instructions, caches	variable, tightly coupled memories, MPU
		ARM966E-S	Thumb, Enhanced DSP instructions	no cache, TCMs
		ARM968E-S	As ARM966E-S	no cache, TCMs
	ARMv5TEJ	ARM926EJ-S	Thumb, Jazelle DBX, Enhanced DSP instructions	variable, TCMs, MMU	220 MIPS @ 200 MHz
	ARMv5TE	ARM996HS	Clockless processor, as ARM966E-S	no caches, TCMs, MPU
ARM10E	ARMv5TE	ARM1020E	6-stage pipeline, Thumb, Enhanced DSP instructions, (VFP)	32 KB/32 KB, MMU
	ARMv5TE	ARM1022E	As ARM1020E	16 KB/16 KB, MMU
	ARMv5TEJ	ARM1026EJ-S	Thumb, Jazelle DBX, Enhanced DSP instructions, (VFP)	variable, MMU or MPU
XScale XScale The XScale, a microprocessor core, is Intel's and Marvell's implementation of the ARMv5 architecture, and consists of several distinct families: IXP, IXC, IOP, PXA and CE . Intel sold the PXA family to Marvell Technology Group in June 2006....	ARMv5TE	XScale	7-stage pipeline, Thumb, Enhanced DSP instructions	32 KB/32 KB, MMU	133–400 MHz
		Bulverde	Wireless MMX, Wireless SpeedStep SpeedStep SpeedStep is a trademark for a series of dynamic frequency scaling technologies built into some Intel microprocessors that allow the clock speed of the processor to be dynamically changed by software... added	32 KB/32 KB, MMU	312–624 MHz
		Monahans	Wireless MMX2 added	32 KB/32 KB (L1), optional L2 cache up to 512 KB, MMU	up to 1.25 GHz
ARM11 ARM11 ARM11 is an ARM architecture 32-bit RISC microprocessor family which introduced the ARMv6 architectural additions. These include SIMD media instructions, multiprocessor support and a new cache architecture...	ARMv6	ARM1136J(F)-S	8-stage pipeline, SIMD SIMD Single instruction, multiple data , is a class of parallel computers in Flynn's taxonomy. It describes computers with multiple processing elements that perform the same operation on multiple data simultaneously... , Thumb, Jazelle DBX, (VFP), Enhanced DSP instructions	variable, MMU	740 @ 532–665 MHz (i.MX31 SoC), 400–528 MHz
	ARMv6T2	ARM1156T2(F)-S	8-stage pipeline, SIMD SIMD Single instruction, multiple data , is a class of parallel computers in Flynn's taxonomy. It describes computers with multiple processing elements that perform the same operation on multiple data simultaneously... , Thumb-2, (VFP), Enhanced DSP instructions	variable, MPU
	ARMv6Z	ARM1176JZ(F)-S	As ARM1136EJ(F)-S	variable, MMU + TrustZone	965 DMIPS @ 772 MHz, up to 2 600 DMIPS with four processors
	ARMv6K	ARM11 MPCore	As ARM1136EJ(F)-S, 1–4 core SMP	variable, MMU
Cortex-A	ARMv7-A	Cortex-A5 (MPCore)	Application profile, ARM / Thumb / Thumb-2 / DSP / SIMD / Optional VFPv3 FPU / Optional NEON / Jazelle RCT and DBX, 1–4 cores / optional MPCore, snoop control unit (SCU), generic interrupt controller (GIC), accelerator coherence port (ACP)	4-64KB / 4-64KB L1, MMU + TrustZone	1.57 DMIPS / MHz per core
		Cortex-A7 MPCore	Application profile, ARM / Thumb / Thumb-2 / DSP / VFPv4 FPU / NEON / Jazelle RCT and DBX / Hardware virtualization, in-order execution, superscalar Superscalar A superscalar CPU architecture implements a form of parallelism called instruction level parallelism within a single processor. It therefore allows faster CPU throughput than would otherwise be possible at a given clock rate... , 1–4 SMP cores, Large Physical Address Extensions (LPAE), snoop control unit (SCU), generic interrupt controller (GIC), ACP, architecure and feature set are identical to A15, 8-10 stage pipeline, low-power design	32KB / 32KB L1, 0-4MB L2, L1 & L2 have Parity & ECC, MMU + TrustZone
		Cortex-A8 ARM Cortex-A8 The ARM Cortex-A8 is a processor core designed by ARM Holdings implementing the ARM v7 instruction set architecture. Compared to the ARM11 core, the Cortex-A8 is dual-issue superscalar, achieving roughly twice the instructions executed per clock cycle....	Application profile, ARM / Thumb / Thumb-2 / VFPv3 FPU / Optional NEON / Jazelle RCT and DAC, 13-stage superscalar Superscalar A superscalar CPU architecture implements a form of parallelism called instruction level parallelism within a single processor. It therefore allows faster CPU throughput than would otherwise be possible at a given clock rate... pipeline	16-32KB / 16-32KB L1, 0-1MB L2 opt ECC, MMU + TrustZone	up to 2 000 (2.0 DMIPS/MHz in speed from 600 MHz to greater than 1 GHz)
		Cortex-A9 MPCore ARM Cortex-A9 MPCore The ARM Cortex-A9 MPCore is a 32-bit multicore processor providing up to 4 cache-coherent Cortex-A9 cores, each implementing the ARM v7 instruction set architecture.-Features:Key features of the Cortex-A9 core are:...	Application profile, ARM / Thumb / Thumb-2 / DSP / Optional VFPv3 FPU / Optional NEON / Jazelle RCT and DBX, out-of-order Out-of-order execution In computer engineering, out-of-order execution is a paradigm used in most high-performance microprocessors to make use of instruction cycles that would otherwise be wasted by a certain type of costly delay... speculative issue Speculative execution Speculative execution in computer systems is doing work, the result of which may not be needed. This performance optimization technique is used in pipelined processors and other systems.-Main idea:... superscalar Superscalar A superscalar CPU architecture implements a form of parallelism called instruction level parallelism within a single processor. It therefore allows faster CPU throughput than would otherwise be possible at a given clock rate... , 1–4 SMP cores, snoop control unit (SCU), generic interrupt controller (GIC), accelerator coherence port (ACP)	16-64KB / 16-64KB L1, 0-8MB L2 opt Parity, MMU + TrustZone	2.5 DMIPS/MHz per core, 10 000 DMIPS @ 2 GHz on Performance Optimized TSMC 40G (dual core)
		Cortex-A15 MPCore ARM Cortex-A15 MPCore The ARM Cortex-A15 MPCore is a multicore ARM architecture processor providing an out-of-order superscalar pipeline ARM v7 instruction set running at up to 2.5 GHz. ARM has confirmed that the Cortex A15 core is 40 percent faster than the Cortex-A9 core, all things equal...	Application profile, ARM / Thumb / Thumb-2 / DSP / VFPv4 FPU / NEON / Jazelle RCT and DBX / Hardware virtualization, out-of-order Out-of-order execution In computer engineering, out-of-order execution is a paradigm used in most high-performance microprocessors to make use of instruction cycles that would otherwise be wasted by a certain type of costly delay... speculative issue Speculative execution Speculative execution in computer systems is doing work, the result of which may not be needed. This performance optimization technique is used in pipelined processors and other systems.-Main idea:... superscalar Superscalar A superscalar CPU architecture implements a form of parallelism called instruction level parallelism within a single processor. It therefore allows faster CPU throughput than would otherwise be possible at a given clock rate... , 1–4 SMP cores, Large Physical Address Extensions (LPAE), snoop control unit (SCU), generic interrupt controller (GIC), ACP, 15-24 stage pipeline	32KB / 32KB L1, 0-4MB L2, L1 & L2 have Parity & ECC, MMU + TrustZone	At least 3.5 DMIPS/MHz per core (Up to 4.01 DMIPS/MHz depending on implementation).
Cortex-R	ARMv7-R	Cortex-R4	Real-time profile, Thumb / Thumb-2 / DSP / optional VFPv3 FPU, optional parity & ECC for internal buses / cache / TCM, 8-stage pipeline dual-core running lockstep with fault logic	0-64KB / 0-64KB, 0-2 of 0-8MB TCM, opt MPU with 8/12 regions
		Cortex-R5 (MPCore)	Real-time profile, Thumb / Thumb-2 / DSP / optional VFPv3 FPU and precision, optional parity & ECC for internal buses / cache / TCM, 8-stage pipeline dual-core running lock-step with fault logic / optional as 2 independent cores, low-latency peripheral port (LLPP), accelerator coherency port (ACP)	0-64KB / 0-64KB, 0-2 of 0-8MB TCM, opt MPU with 12/16 regions
		Cortex-R7 (MPCore)	Real-time profile, Thumb / Thumb-2 / DSP / optional VFPv3 FPU and precision, optional parity & ECC for internal buses / cache / TCM, 11-stage pipeline dual-core running lock-step with fault logic / out-of-order execution / dynamic register renaming Register renaming In computer architecture, register renaming refers to a technique used to avoid unnecessary serialization of program operations imposed by the reuse of registers by those operations.-Problem definition:... / optional as 2 independent cores, low-latency peripheral port (LLPP), ACP	0-64KB / 0-64KB, ? of 0-128KB TCM, opt MPU with 16 regions
Cortex-M	ARMv6-M	Cortex-M0	Microcontroller profile, Thumb + Thumb-2 subset (BL, MRS, MSR, ISB, DSB, DMB), hardware multiply instruction, optional system timer, no bit-banding memory	No cache, No TCM, No MPU	0.9 DMIPS/MHz
	ARMv6-M	Cortex-M1	Microcontroller profile, Thumb + Thumb-2 subset (BL, MRS, MSR, ISB, DSB, DMB), hardware multiply instruction (optional small), OS option adds SVC / banked stack pointer / system timer, no bit-banding memory	No cache, 0-1024KB I-TCM, 0-1024KB D-TCM, No MPU	136 DMIPS @ 170 MHz, (0.8 DMIPS/MHz FPGA-dependent)
	ARMv7-M	Cortex-M3	Microcontroller profile, Thumb / Thumb-2, hardware multiply and divide instructions, optional bit-banding memory	No cache, No TCM, opt MPU with 8 regions	1.25 DMIPS/MHz
	ARMv7-ME	Cortex-M4	Microcontroller profile, Thumb / Thumb-2 / DSP / optional FPv4 single-precision FPU, hardware multiply and divide instructions, optional bit-banding memory	No cache, No TCM, opt MPU with 8 regions	1.25 DMIPS/MHz
ARM Family	ARM Architecture	ARM Core	Feature	Cache (I/D), MMU Memory management unit A memory management unit , sometimes called paged memory management unit , is a computer hardware component responsible for handling accesses to memory requested by the CPU...	Typical MIPS @ MHz

ARM microprocessor cores

Further reading