ARM Cortex-A15 MPCore
Encyclopedia
The ARM Cortex-A15 MPCore is a multicore ARM architecture
ARM architecture
ARM is a 32-bit reduced instruction set computer instruction set architecture developed by ARM Holdings. It was named the Advanced RISC Machine, and before that, the Acorn RISC Machine. The ARM architecture is the most widely used 32-bit ISA in numbers produced...

 processor providing an out-of-order
Out-of-order execution
In computer engineering, out-of-order execution is a paradigm used in most high-performance microprocessors to make use of instruction cycles that would otherwise be wasted by a certain type of costly delay...

 superscalar
Superscalar
A superscalar CPU architecture implements a form of parallelism called instruction level parallelism within a single processor. It therefore allows faster CPU throughput than would otherwise be possible at a given clock rate...

 pipeline ARM v7 instruction set  running at up to 2.5 GHz. ARM has confirmed that the Cortex A15 core is 40 percent faster than the Cortex-A9
ARM Cortex-A9 MPCore
The ARM Cortex-A9 MPCore is a 32-bit multicore processor providing up to 4 cache-coherent Cortex-A9 cores, each implementing the ARM v7 instruction set architecture.-Features:Key features of the Cortex-A9 core are:...

 core, all things equal. The first A15 designs taped out in the fall of 2011, but products based on the chip are not expected in the market until 2012.

Features

Key features of the Cortex-A15 core are:
  • 40-bit Large Physical Address Extensions (LPAE) addressing up to 1 TB of RAM.
  • 15 stage integer / 17-25 stage floating point pipeline, with out-of-order
    Out-of-order execution
    In computer engineering, out-of-order execution is a paradigm used in most high-performance microprocessors to make use of instruction cycles that would otherwise be wasted by a certain type of costly delay...

     speculative issue
    Speculative execution
    Speculative execution in computer systems is doing work, the result of which may not be needed. This performance optimization technique is used in pipelined processors and other systems.-Main idea:...

     3-way superscalar
    Superscalar
    A superscalar CPU architecture implements a form of parallelism called instruction level parallelism within a single processor. It therefore allows faster CPU throughput than would otherwise be possible at a given clock rate...

     execution pipeline.
  • 4 cores per cluster, up to 2 clusters per chip with CoreLink 400 (an AMBA-4 coherent interconnect). ARM provides specifications but the foundries individually design ARM chips, and AMBA-4 scales beyond 2 clusters.
  • DSP and NEON SIMD
    SIMD
    Single instruction, multiple data , is a class of parallel computers in Flynn's taxonomy. It describes computers with multiple processing elements that perform the same operation on multiple data simultaneously...

     extensions onboard (per core).
  • VFPv4 Floating Point Unit onboard (per core).
  • Hardware virtualization support.
  • Thumb-2 instruction set encoding reduces the size of programs with little impact on performance.
  • TrustZone security extensions.
  • Jazelle
    Jazelle
    Jazelle DBX allows some ARM processors to execute Java bytecode in hardware as a third execution state alongside the existing ARM and Thumb modes. Jazelle functionality was specified in the ARMv5TEJ architecture and the first processor with Jazelle technology was the ARM926EJ-S...

     DBX support for Java execution.
  • Jazelle RCT for JIT compilation.
  • Program Trace Macrocell and CoreSight Design Kit for unobtrusive tracing of instruction execution.
  • 32kB data + 32kB instruction L1 cache per core.
  • Integrated low-latency level-2 cache controller, up to 4 MB per cluster.

Implementations

Implementations are only expected to sample in 2011, and none are expected to market before 2012 or 2013.

Press announcements of forthcoming implementations:
  • Broadcom SoC
  • Texas Instruments OMAP
    OMAP
    OMAP developed by Texas Instruments is a category of proprietary system on chips for portable and mobile multimedia applications. OMAP devices generally include a general-purpose ARM architecture processor core plus one or more specialized co-processors...

     5 SoCs
  • ST-Ericsson Nova A9600
  • Nvidia a future Tegra
    Tegra
    Tegra developed by Nvidia is a system-on-a-chip series for mobile devices such as smartphones, personal digital assistants, and mobile Internet devices. The Tegra integrates the ARM architecture processor central processing unit , graphics processing unit , northbridge, southbridge, and memory...

     chip
  • Samsung Exynos 5250

Other licensees expected to produce an A15 design at some point are LG and Samsung. Although Apple is a major ARM licensee with already substantial developed ARM-based product lines (the iPad, iPhone, and iPods), no announcements have yet been made about a continuation in the form of a future cortex A15-based Apple design. It should be noted that Apple never makes any announcements regarding its future products or roadmaps.

See also

  • ARM Holdings
    ARM Holdings
    ARM Holdings plc is a British multinational semiconductor and software company headquartered in Cambridge. Its largest business is in processors, although it also designs, licenses and sells software development tools under the RealView and KEIL brands, systems and platforms, system-on-a-chip...

  • ARM architecture
    ARM architecture
    ARM is a 32-bit reduced instruction set computer instruction set architecture developed by ARM Holdings. It was named the Advanced RISC Machine, and before that, the Acorn RISC Machine. The ARM architecture is the most widely used 32-bit ISA in numbers produced...

  • ARM Cortex-A8
    ARM Cortex-A8
    The ARM Cortex-A8 is a processor core designed by ARM Holdings implementing the ARM v7 instruction set architecture. Compared to the ARM11 core, the Cortex-A8 is dual-issue superscalar, achieving roughly twice the instructions executed per clock cycle....

  • ARM Cortex-A9 MPCore
    ARM Cortex-A9 MPCore
    The ARM Cortex-A9 MPCore is a 32-bit multicore processor providing up to 4 cache-coherent Cortex-A9 cores, each implementing the ARM v7 instruction set architecture.-Features:Key features of the Cortex-A9 core are:...

  • List of ARM microprocessor cores

External links

The source of this article is wikipedia, the free encyclopedia.  The text of this article is licensed under the GFDL.
 
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