16 nanometer
Encyclopedia
The 16 nanometer
(16 nm) node is the technology node following the 22 nm
node. The exact naming of the technology nodes comes from the International Technology Roadmap for Semiconductors
(ITRS). By conservative ITRS estimates the 16 nm technology is projected to be reached by semiconductor companies in the 2014 timeframe. It has been claimed that transistors cannot be scaled below the size achievable at 16 nm due to quantum tunnelling
, regardless of the materials used. As of 2009, leading companies are working on 22 nm development. However, in complying with its own "Architecture and Silicon Cadence Model
", Intel will need to reach a new manufacturing process every two years; this would imply going to 16 nm node as early as 2013. However, for Intel, the design rule at this node designation is actually about 30 nm.
16 nm resolution is difficult to achieve in a polymeric resist
, even with electron beam lithography
. In addition, the chemical effects of ionizing radiation
also limit reliable resolution to about 30 nm
, which is also achievable using current state-of-the-art immersion lithography
. Hardmask
materials and possibly iterated double patterning
will be required.
A more significant limitation comes from plasma damage to low-k materials. The extent of damage is typically 20 nm thick, but can also go up to about 100 nm. The damage sensitivity is expected to get worse as the low-k materials become more porous.
For comparison, the lattice constant
, or distance between surface atoms, of unstrained silicon is 543 pm
(0.543 nm). Thus fewer than thirty atoms would span the channel length, leading to substantial leakage
.
Tela Innovations and Sequoia Design Systems have developed a methodology allowing double exposure for the 16 nm node.
Samsung and Synopsys have also begun implementing double patterning in 22 nm and 16 nm design flows.
Mentor Graphics reported taping out 16 nm test chips in 2010.
On January 17, 2011, IBM announced that they are teaming up with ARM to develop 14 nm chip processing technology.
On February 18, 2011, Intel announced that it will construct a new $5 billion fab in Arizona, designed to manufacture chips using 14 nm manufacturing processes and leading-edge 300 mm wafers. The new lab will be named Fab 42, and construction will start in the middle of 2011, Intel said in a statement Friday. Intel billed the new facility as "the most advanced, high-volume manufacturing facility in the world," and said it would come on line in 2013.
On May 17, 2011, Intel announced a roadmap for 2014 that includes 14 nm transistors for their Xeon, CORE, and Atom product lines.
demonstrated 15 nm gate length and 10 nm fin
width using a sidewall spacer process. It has been suggested that for the 16 nm node, a logic transistor would have a gate length of about 5 nm.
In December 2007, Toshiba demonstrated a prototype memory unit that uses 15 nanometer thin lines.
In December 2009, National Nano Device Laboratories, part of the Taiwan
ese government, produced a 16 nm SRAM chip.
In September 2011, Hynix announced the development of 15 nm NAND cells.
Nanometre
A nanometre is a unit of length in the metric system, equal to one billionth of a metre. The name combines the SI prefix nano- with the parent unit name metre .The nanometre is often used to express dimensions on the atomic scale: the diameter...
(16 nm) node is the technology node following the 22 nm
22 nanometer
The 22 nanometer node is the CMOS process step following 32 nm. It was introduced by semiconductor companies in 2011. The typical half-pitch for a memory cell is around 22 nm...
node. The exact naming of the technology nodes comes from the International Technology Roadmap for Semiconductors
International Technology Roadmap for Semiconductors
The International Technology Roadmap for Semiconductors is a set of documents produced by a group of semiconductor industry experts. These experts are representative of the sponsoring organisations which include the Semiconductor Industry Associations of the US, Europe, Japan, South Korea and...
(ITRS). By conservative ITRS estimates the 16 nm technology is projected to be reached by semiconductor companies in the 2014 timeframe. It has been claimed that transistors cannot be scaled below the size achievable at 16 nm due to quantum tunnelling
Quantum tunnelling
Quantum tunnelling refers to the quantum mechanical phenomenon where a particle tunnels through a barrier that it classically could not surmount. This plays an essential role in several physical phenomena, such as the nuclear fusion that occurs in main sequence stars like the sun, and has important...
, regardless of the materials used. As of 2009, leading companies are working on 22 nm development. However, in complying with its own "Architecture and Silicon Cadence Model
Intel Tick-Tock
"Tick-Tock" is a model, of Jones Farm 5 and adopted by chip manufacturer Intel Corporation since 2007 to follow every microarchitectural change with shrinking of the process technology. Every "tick" is a shrinking of process technology of the previous microarchitecture and every "tock" is a new...
", Intel will need to reach a new manufacturing process every two years; this would imply going to 16 nm node as early as 2013. However, for Intel, the design rule at this node designation is actually about 30 nm.
16 nm resolution is difficult to achieve in a polymeric resist
Resist
In semiconductor fabrication, a resist is a thin layer used to transfer a circuit pattern to the semiconductor substrate which it is deposited upon. A resist can be patterned via lithography to form a micrometer-scale, temporary mask that protects selected areas of the underlying substrate during...
, even with electron beam lithography
Electron beam lithography
Electron beam lithography is the practice of emitting a beam of electrons in a patterned fashion across a surface covered with a film , and of selectively removing either exposed or non-exposed regions of the resist...
. In addition, the chemical effects of ionizing radiation
Ionizing radiation
Ionizing radiation is radiation composed of particles that individually have sufficient energy to remove an electron from an atom or molecule. This ionization produces free radicals, which are atoms or molecules containing unpaired electrons...
also limit reliable resolution to about 30 nm
Extreme ultraviolet lithography
Extreme ultraviolet lithography is a next-generation lithography technology using an extreme ultraviolet wavelength, currently expected to be 13.5 nm.-EUVL light source:...
, which is also achievable using current state-of-the-art immersion lithography
Immersion lithography
Immersion lithography is a photolithography resolution enhancement technique for manufacturing integrated circuits that replaces the usual air gap between the final lens and the wafer surface with a liquid medium that has a refractive index greater than one. The resolution is increased by a factor...
. Hardmask
Hardmask
A hardmask is a material used in semiconductor processing as an etch mask in lieu of polymer or other organic "soft" resist materials. The idea is that polymers tend to be etched easily by oxygen, fluorine, chlorine or other reactive gases to the extent that a pattern defined using polymeric mask...
materials and possibly iterated double patterning
Double patterning
Multiple patterning is a class of technologies for manufacturing integrated circuits , developed for photolithography to enhance the feature density. The simplest case of multiple patterning is double patterning, where a conventional lithography process is enhanced to produce double the expected...
will be required.
A more significant limitation comes from plasma damage to low-k materials. The extent of damage is typically 20 nm thick, but can also go up to about 100 nm. The damage sensitivity is expected to get worse as the low-k materials become more porous.
For comparison, the lattice constant
Lattice constant
The lattice constant [or lattice parameter] refers to the constant distance between unit cells in a crystal lattice. Lattices in three dimensions generally have three lattice constants, referred to as a, b, and c. However, in the special case of cubic crystal structures, all of the constants are...
, or distance between surface atoms, of unstrained silicon is 543 pm
Picometre
A picometre is a unit of length in the metric system, equal to one trillionth, i.e. of a metre, which is the current SI base unit of length...
(0.543 nm). Thus fewer than thirty atoms would span the channel length, leading to substantial leakage
Leakage (semiconductors)
In semiconductor devices, leakage is a quantum phenomenon where mobile charge carriers tunnel through an insulating region. Leakage increases exponentially as the thickness of the insulating region decreases. Tunneling leakage can also occur across semiconductor junctions between heavily doped...
.
Tela Innovations and Sequoia Design Systems have developed a methodology allowing double exposure for the 16 nm node.
Samsung and Synopsys have also begun implementing double patterning in 22 nm and 16 nm design flows.
Mentor Graphics reported taping out 16 nm test chips in 2010.
On January 17, 2011, IBM announced that they are teaming up with ARM to develop 14 nm chip processing technology.
On February 18, 2011, Intel announced that it will construct a new $5 billion fab in Arizona, designed to manufacture chips using 14 nm manufacturing processes and leading-edge 300 mm wafers. The new lab will be named Fab 42, and construction will start in the middle of 2011, Intel said in a statement Friday. Intel billed the new facility as "the most advanced, high-volume manufacturing facility in the world," and said it would come on line in 2013.
On May 17, 2011, Intel announced a roadmap for 2014 that includes 14 nm transistors for their Xeon, CORE, and Atom product lines.
Technology demos
In 2005, ToshibaToshiba
is a multinational electronics and electrical equipment corporation headquartered in Tokyo, Japan. It is a diversified manufacturer and marketer of electrical products, spanning information & communications equipment and systems, Internet-based solutions and services, electronic components and...
demonstrated 15 nm gate length and 10 nm fin
Fin (extended surface)
In the study of heat transfer, a fin is a surface that extends from an object to increase the rate of heat transfer to or from the environment by increasing convection. The amount of conduction, convection, or radiation of an object determines the amount of heat it transfers...
width using a sidewall spacer process. It has been suggested that for the 16 nm node, a logic transistor would have a gate length of about 5 nm.
In December 2007, Toshiba demonstrated a prototype memory unit that uses 15 nanometer thin lines.
In December 2009, National Nano Device Laboratories, part of the Taiwan
Taiwan
Taiwan , also known, especially in the past, as Formosa , is the largest island of the same-named island group of East Asia in the western Pacific Ocean and located off the southeastern coast of mainland China. The island forms over 99% of the current territory of the Republic of China following...
ese government, produced a 16 nm SRAM chip.
In September 2011, Hynix announced the development of 15 nm NAND cells.