XCore XS1-G4
Encyclopedia
The XS1-G4 is a processor
designed by XMOS
. It is a 32-bit quad-core processor, where each core runs up to 8 concurrent threads. It was available as of Autumn 2008 running at 400 MHz. Each thread can run at up to 100 MHz; four threads follow each other through the pipeline
, resulting in a top speed of 1.6 GIPS for four cores if 16 threads are running. The XS1-G4 is a distributed memory
multi core processor, requiring the end user and compiler
to deal with data distribution. When more than 4 threads execute, the 400 MIPS of each core is equally distributed over all active threads. This allows the use of extra threads in order to hide latency.
, a virtual connection between two threads. Channels are supported between threads on a core, between cores on a single chip through a XSwitch
, or between cores in the same system if the switches are connected by means of physical links.
The instruction set is a load-store instruction set.
All instructions execute in a single cycle. If an instruction does not need data from memory (for example, arithmetic operations), the instruction will prefetch a word of instructions.This acts like a very small instruction cache, but its behavior can be predicted at compile time
, making timing behavior as predictable as functional behavior. The instruction set natively supports events
which enables the processor to stop a thread and restart it when an event is ready. In addition, a thread may be interrupted in order to deal with some external events.
The total number of data pins on an XS1-G4 is 256, requiring a 512-pin BGA to bring out all pins (including ground, power, and system pins). The 144 pin BGA only brings out 48 pins of two cores, effectively providing two cores for processing only, and two cores for both processing and I/O.
Microprocessor
A microprocessor incorporates the functions of a computer's central processing unit on a single integrated circuit, or at most a few integrated circuits. It is a multipurpose, programmable device that accepts digital data as input, processes it according to instructions stored in its memory, and...
designed by XMOS
XMOS
XMOS is a fabless semiconductor company that develops multi-core multi-threaded processors designed to execute several real-time tasks, DSP, and control flow all at once.-Company history:...
. It is a 32-bit quad-core processor, where each core runs up to 8 concurrent threads. It was available as of Autumn 2008 running at 400 MHz. Each thread can run at up to 100 MHz; four threads follow each other through the pipeline
Instruction pipeline
An instruction pipeline is a technique used in the design of computers and other digital electronic devices to increase their instruction throughput ....
, resulting in a top speed of 1.6 GIPS for four cores if 16 threads are running. The XS1-G4 is a distributed memory
Distributed memory
In computer science, distributed memory refers to a multiple-processor computer system in which each processor has its own private memory. Computational tasks can only operate on local data, and if remote data is required, the computational task must communicate with one or more remote processors...
multi core processor, requiring the end user and compiler
Compiler
A compiler is a computer program that transforms source code written in a programming language into another computer language...
to deal with data distribution. When more than 4 threads execute, the 400 MIPS of each core is equally distributed over all active threads. This allows the use of extra threads in order to hide latency.
Description
The XS1-G4 comprises four cores and a switch. Each core has a data path, a memory, and register banks for eight threads. Threads running on different cores can communicate with each other by exchanging messages through the switches. Switches of multiple G4s can be connected together to form a larger system. The instruction set supports the notion of a channelChannel (communications)
In telecommunications and computer networking, a communication channel, or channel, refers either to a physical transmission medium such as a wire, or to a logical connection over a multiplexed medium such as a radio channel...
, a virtual connection between two threads. Channels are supported between threads on a core, between cores on a single chip through a XSwitch
XSwitch
The XSwitch is an interconnect used by the XCore processor. The interconnect protocol is defined by XMOS, and is based around routing messages comprising 9-bit tokens between cores on a network...
, or between cores in the same system if the switches are connected by means of physical links.
Instruction Set Architecture
Each thread has access to 12 general purpose registers, and a standard 3-operand instruction set is used for programming the thread. The instruction set is encoded densely, encoding most instructions in 16 bits, where 11 bits are used for specifying 3 operands, and 5 bits are used to encode the opcode. Less frequently used instructions are encoded in 32 bits.The instruction set is a load-store instruction set.
All instructions execute in a single cycle. If an instruction does not need data from memory (for example, arithmetic operations), the instruction will prefetch a word of instructions.This acts like a very small instruction cache, but its behavior can be predicted at compile time
Compile time
In computer science, compile time refers to either the operations performed by a compiler , programming language requirements that must be met by source code for it to be successfully compiled , or properties of the program that can be reasoned about at compile time.The operations performed at...
, making timing behavior as predictable as functional behavior. The instruction set natively supports events
Event (computing)
In computing an event is an action that is usually initiated outside the scope of a program and that is handled by a piece of code inside the program. Typically events are handled synchronous with the program flow, that is, the program has one or more dedicated places where events are handled...
which enables the processor to stop a thread and restart it when an event is ready. In addition, a thread may be interrupted in order to deal with some external events.
Resources
Each core on the XS1-G4 has access to:- 64 KByte of RAMRam-Animals:*Ram, an uncastrated male sheep*Ram cichlid, a species of freshwater fish endemic to Colombia and Venezuela-Military:*Battering ram*Ramming, a military tactic in which one vehicle runs into another...
- 64 I/O pins that can be accessed using 28 ports: 16 ports access 16 single pins, the other 12 ports access nibbles, bytes, and words of pins.
- 32 channel ends; each channel end can be connected to another channel end setting up a uni directional communication path. Two channels can be set up to point to each other creating a bi directional path.
- 10 timers
The total number of data pins on an XS1-G4 is 256, requiring a 512-pin BGA to bring out all pins (including ground, power, and system pins). The 144 pin BGA only brings out 48 pins of two cores, effectively providing two cores for processing only, and two cores for both processing and I/O.