In a 1996–2004 research project in the Computer Science Division of the University of California, Berkeley, The Berkeley IRAM Project explored computer architecture

Computer architecture

In computer science and engineering, computer architecture is the practical art of selecting and interconnecting hardware components to create computers that meet functional, performance and cost goals and the formal modelling of those systems....

 enabled by the wide bandwidth between memory and processor made possible when both are designed on the same integrated circuit

Integrated circuit

An integrated circuit or monolithic integrated circuit is an electronic circuit manufactured by the patterned diffusion of trace elements into the surface of a thin substrate of semiconductor material...

 (chip). Since it was envisioned that such a chip would consist primarily of random-access memory

Random-access memory

Random access memory is a form of computer data storage. Today, it takes the form of integrated circuits that allow stored data to be accessed in any order with a worst case performance of constant time. Strictly speaking, modern types of DRAM are therefore not random access, as data is read in...

 (RAM), with a smaller part needed for the central processing unit

Central processing unit

The central processing unit is the portion of a computer system that carries out the instructions of a computer program, to perform the basic arithmetical, logical, and input/output operations of the system. The CPU plays a role somewhat analogous to the brain in the computer. The term has been in...

 (CPU), the research team used the term “Intelligent RAM” (or IRAM) to describe a chip with this architecture. Like the J–Machine

J–Machine

The J–Machine is a parallel computer designed by the MIT Concurrent VLSI Architecture group in conjunction with the Intel Corporation...

 project at MIT, the primary objective of the research was to avoid the Von Neumann bottleneck which occurs when the connection between memory and CPU is a relatively narrow memory bus

Memory bus

The memory bus is the computer bus which connects the main memory to the memory controller in computer systems. Originally, general-purpose buses like VMEbus and the S-100 bus were used, but to reduce latency, modern memory buses are designed to connect directly to DRAM chips, and thus are...

 between separate integrated circuits.

Theory

With strong competitive pressures, the technology employed for each component of a computer system—principally CPU, memory, and offline storage—is typically selected to minimize the cost needed to attain a given level of performance. Though both microprocessor and memory are implemented as integrated circuits, the prevailing technology used for each differs; microprocessor technology optimizes speed and memory technology optimizes density. For this reason, the integration of memory and processor in the same chip has (for the most part) been limited to static random-access memory (SRAM), which may be implemented using circuit technology optimized for logic performance, rather than the denser and lower-cost dynamic random-access memory (DRAM), which is not. Microprocessor access to off-chip memory costs time and power, however, significantly limiting processor performance. For this reason computer architecture employing a hierarchy of memory systems has developed, in which static memory is integrated with the microprocessor for temporary, easily accessible storage (or cache) of data which is also retained off-chip in DRAM. Since the on-chip cache memory is redundant, its presence adds to cost and power. The purpose of the IRAM research project was to find if (in some computing applications) a better trade-off between cost and performance could be achieved with an architecture in which DRAM was integrated on-chip with the processor, thus eliminating the need for a redundant static memory cache – even though the technology used was not optimum for DRAM implementation.

Participants

Faculty participants in the IRAM project included:

• Prof. David Patterson, also known for Berkeley RISC
  Berkeley RISC
  Berkeley RISC was one of two seminal research projects into RISC-based microprocessor design taking place under ARPA's VLSI project. RISC was led by David Patterson at the University of California, Berkeley between 1980 and 1984, while the other was taking place only a short drive away at Stanford...
  
  
• Kathy Yelick
• John Kubiatowicz

Graduate participants included:

• Krste Aasanovic (later professor at Berkeley
  University of California, Berkeley
  The University of California, Berkeley , is a teaching and research university established in 1868 and located in Berkeley, California, USA...
  
  )
• Christoforos Kozyrakis (later professor at Stanford
  Stanford University
  The Leland Stanford Junior University, commonly referred to as Stanford University or Stanford, is a private research university on an campus located near Palo Alto, California. It is situated in the northwestern Santa Clara Valley on the San Francisco Peninsula, approximately northwest of San...
  
  )

Contribution

While it is fair to say that Berkeley IRAM did not achieve the recognition that Berkeley RISC

Berkeley RISC

Berkeley RISC was one of two seminal research projects into RISC-based microprocessor design taking place under ARPA's VLSI project. RISC was led by David Patterson at the University of California, Berkeley between 1980 and 1984, while the other was taking place only a short drive away at Stanford...

received,
the IRAM project was nevertheless influential.
Although initial IRAM proposals focused on trade-offs between CPU and DRAM, IRAM research came to concentrate on vector instruction sets.
Its publications were early advocates of the incorporation of vector processing and vector instruction sets into microprocessors, and several commercial microprocessors, such as the Intel AVX, subsequently adopted vector processing instruction set extensions.

External links

• The Berkeley IRAM Project
• Berkeley IRAM Project publication list