SGI Challenge
Encyclopedia
The Challenge, code-named Eveready (deskside models) and Terminator (rackmount models), is a family of server computers
and supercomputer
s developed and manufactured by Silicon Graphics
in the early to mid-1990s that succeeded the earlier Power (not to be confused with the IBM POWER
) series systems. The Challenge was later succeeded by the NUMAlink
-based Origin 200
and Origin 2000
in 1996.
, the Challenge was upgraded to support more processors and memory as well as featuring support for this new processor. Such systems are known as the "POWER Challenge". During the final years of the Challenge architecture's useful life, the line was upgraded to support R10000
microprocessors. Older Challenge systems using the R10000 were known as the "Challenge 10000", while the newer POWER Challenge systems using the R10000 were known as the "POWER Challenge 10000".
Models suffixed with "GR" (for "Graphics Ready") could support the RealityEngine
and InfiniteReality
graphics subsystems. Standard models were either servers or supercomputers with no graphics support.
. At the time of its announcement, Silicon Graphics claimed that the POWER Challenge would have the same level of performance as Cray's Cray Y-MP
with a single microprocessor. The new model was introduced in the middle of 1994 and used the MIPS R8000
microprocessor chip set, which consisted of the R8000 microprocessor and R8010 floating point unit
accompanied by a "streaming" cache and its associated controllers. Much of the POWER Challenge's performance depended on the R8000, a microprocessor intended to achieve supercomputing performance and designed for floating-point scientific applications. As a result, the R8000 had features such as fused multiply–add instructions and a large cache.
In 1995, Silicon Graphics upgraded the POWER Challenge with R8000 microprocessors clocked at 90 MHz, enabling the system to scale up to 6.48 GFLOPS, an improvement of 1 GFLOPS over the previous R8000 microprocessor clocked at 75 MHz.
microprocessor. These models were introduced in January 1996, succeeding the R4400-based Challenge and the R8000-based POWER Challenge, although such systems co-existed with the POWER Challenge 10000 for some time. To support the new R10000s, a new CPU board, the "IP25" was introduced. The new CPU board, like previous IP19 CPU board, support four processors each and their associated secondary caches.
of Challenge or POWER Challenge servers respectively. The CHALLENGEarray supports 2 to 288 R10000
processors while the POWER CHALLENGEarray supports 2 to 144 R8000 processors and up to 128 GB of memory. The POWER CHALLENGEarray was introduced on 15 November 1994.
workstation
s that were not configured with the graphics hardware that made them useful as workstations. These systems were Challenges in name only and have no architectural similarity with the multiprocessing Challenges, although they had cases with the same blue hue as proper Challenges. They were branded as such in order for the systems to be marketed as part of the Challenge server family, positioned as entry level servers.
Rackmount systems have a 1,900 watt power supply.
multiprocessor
computer. The system is based on nodes, which are implemented as boards
that plug into a midplane containing Ebus slots and the POWERpath-2 "Ebus" bus, a system bus that the nodes use to communicate with other nodes. The POWERpath-2 bus consists of a 256-bit path for data and a 40-bit path for addressing clocked at 47.6 MHz (21-nanosecond cycle), providing 1.2 GB/s of sustained bandwidth.
The midplane in DM and L models contains five Ebus slots that can support a combination of three CPU, one memory or two POWERchannel-2 interface boards. The midplane also contains five VME
expansion slots.
The midplane in XL models contains fifteen Ebus slots that can support a combination of nine CPU, eight memory or five POWERchannel-2 interface boards. The midplane also contains six VME expansion slots and three power board slots.
(SIMM) slots and two leaf controllers. Fast page mode (FPM) error correcting code (ECC) SIMMs with capacities of 16 MB (known as the "high-density" SIMM) and 64 MB (known as the "super-density" SIMM) are supported, enables the board to provide 64 MB to 2 GB of memory. The SIMMs are installed in groups of four.
The memory is organized into eight banks, with four banks forming a leaf. The memory can be interleaved if there are two or more leaves present in the system. The memory bus is 576-bit wide, with a 512-bit path for data and a 64-bit path for ECC. The memory is controlled by the two leaf controllers. Each leaf controller manages four banks of memory and half of a memory transaction. It is therefore connected to 256 bits of the memory bus and 128 bits of the POWERpath-2 bus.
Memory transactions are 128-byte wide, the same width as the cache line of the MIPS microprocessors used. A memory read is completed in two cycles of the memory clock, and is buffered by the leaf controllers before it is placed in a sent over the POWERpath-2 bus in four cycles of the POWERpath-2 bus clock.
The SIMMs are protected by ECC, and the ECC implementation can correct single-bit errors and detect double-bit errors. The SIMMs also contain built-in self-test circuitry, which tests the SIMM during power on or reset and alerts the firmware, which disables the bank(s) of memory containing faulty SIMM(s), if faults are detected.
Server (computing)
In the context of client-server architecture, a server is a computer program running to serve the requests of other programs, the "clients". Thus, the "server" performs some computational task on behalf of "clients"...
and supercomputer
Supercomputer
A supercomputer is a computer at the frontline of current processing capacity, particularly speed of calculation.Supercomputers are used for highly calculation-intensive tasks such as problems including quantum physics, weather forecasting, climate research, molecular modeling A supercomputer is a...
s developed and manufactured by Silicon Graphics
Silicon Graphics
Silicon Graphics, Inc. was a manufacturer of high-performance computing solutions, including computer hardware and software, founded in 1981 by Jim Clark...
in the early to mid-1990s that succeeded the earlier Power (not to be confused with the IBM POWER
IBM POWER
POWER is a reduced instruction set computer instruction set architecture developed by IBM. The name is an acronym for Performance Optimization With Enhanced RISC....
) series systems. The Challenge was later succeeded by the NUMAlink
NUMAlink
NUMAlink is a system interconnect developed by SGI for use in its distributed shared memory ccNUMA computer systems. NUMAlink was originally developed by SGI for their Origin 2000 and Onyx2 systems...
-based Origin 200
SGI Origin 200
The SGI Origin 200, code named Speedo, is an entry-level server computer developed and manufactured by SGI, introduced in October 1996 to accompany their mid-range and high-end Origin 2000. It is based on the same architecture as the Origin 2000 but has an unrelated hardware implementation...
and Origin 2000
SGI Origin 2000
The SGI Origin 2000, code named Lego, is a family of mid-range and high-end servers developed and manufactured by SGI and introduced in 1996 to succeed the SGI Challenge and POWER Challenge. At the time of introduction, these systems ran IRIX 6.4 and later, IRIX 6.5. A variant of the Origin 2000...
in 1996.
Models
There are three distinctive models of the Challenge. The first model, simply known as the "Challenge" used the 64-bit R4400. With the introduction of the R8000R8000
The R8000 is a microprocessor chipset developed by MIPS Technologies, Inc. , Toshiba, and Weitek. It was the first implementation of the MIPS IV instruction set architecture. The R8000 is also known as the TFP, for Tremendous Floating-Point, its name during development.-History:Development of the...
, the Challenge was upgraded to support more processors and memory as well as featuring support for this new processor. Such systems are known as the "POWER Challenge". During the final years of the Challenge architecture's useful life, the line was upgraded to support R10000
R10000
The R10000, code-named "T5", is a RISC microprocessor implementation of the MIPS IV instruction set architecture developed by MIPS Technologies, Inc. , then a division of Silicon Graphics, Inc. . The chief designers were Chris Rowen and Kenneth C. Yeager...
microprocessors. Older Challenge systems using the R10000 were known as the "Challenge 10000", while the newer POWER Challenge systems using the R10000 were known as the "POWER Challenge 10000".
Models suffixed with "GR" (for "Graphics Ready") could support the RealityEngine
RealityEngine
RealityEngine refers to a 3D graphics hardware architecture and a family of graphics systems that implemented the aforementioned hardware architecture that was developed and manufactured by Silicon Graphics during the early to mid 1990s...
and InfiniteReality
InfiniteReality
InfiniteReality refers to a 3D graphics hardware architecture and a family of graphics systems that implemented the aforementioned hardware architecture that was developed and manufactured by Silicon Graphics from 1996 to 2005...
graphics subsystems. Standard models were either servers or supercomputers with no graphics support.
Challenge
| Model | # of CPUs | CPU | CPU MHz | L2 cache | Memory | Enclosure | Introduced | Discontinued |
|---|---|---|---|---|---|---|---|---|
| DM (Departmental) |
1, 2 or 4 | R4400 | 100, 150, 200 or 250 |
1 MB | ? | Deskside | ? | ? |
| L (Large) |
2, 4, 8 or 12 | R4400 | 100, 150, 200 250 |
1 or 4 MB | 2 GB | Deskside | ? | ? |
| GR (Graphics Ready) |
2, 4, 8, 12, 16 or 24 | R4400 | 100, 150, 200 250 |
1 or 4 MB | ? | ? | ? | ? |
| XL (Extra Large) |
2, 4, 8, 12, 16, 24 or 36 | R4400 | 100, 150, 200 or 250 | 1 or 4 MB | 16 GB | Rackmount | ? | ? |
Challenge 10000
| Model | # of CPUs | CPU | CPU MHz | L2 cache | Memory | Chassis | Introduced | Discontinued |
|---|---|---|---|---|---|---|---|---|
| L (Large) |
2, 4, 8 or 12 | R10000 | 195 | 1 or 2 MB | 2 GB | Deskside | ? | ? |
| GR (Graphics Ready) |
2, 4, 8, 12, 16 or 24 | R10000 | 195 | 1 or 2 MB | ? | ? | ? | ? |
| XL (Extra Large) |
2, 4, 8, 12, 16, 24 or 36 | R10000 | 195 | 1 or 2 MB | 16 GB | Rackmount | ? | ? |
POWER Challenge
The POWER Challenge was announced on 28 January 1993 and was intended to compete against supercomputer companies such as Cray ResearchCray
Cray Inc. is an American supercomputer manufacturer based in Seattle, Washington. The company's predecessor, Cray Research, Inc. , was founded in 1972 by computer designer Seymour Cray. Seymour Cray went on to form the spin-off Cray Computer Corporation , in 1989, which went bankrupt in 1995,...
. At the time of its announcement, Silicon Graphics claimed that the POWER Challenge would have the same level of performance as Cray's Cray Y-MP
Cray Y-MP
The Cray Y-MP was a supercomputer sold by Cray Research from 1988, and the successor to the company's X-MP. The Y-MP retained software compatibility with the X-MP, but extended the address registers from 24 to 32 bits. High-density VLSI ECL technology was used and a new liquid cooling system was...
with a single microprocessor. The new model was introduced in the middle of 1994 and used the MIPS R8000
R8000
The R8000 is a microprocessor chipset developed by MIPS Technologies, Inc. , Toshiba, and Weitek. It was the first implementation of the MIPS IV instruction set architecture. The R8000 is also known as the TFP, for Tremendous Floating-Point, its name during development.-History:Development of the...
microprocessor chip set, which consisted of the R8000 microprocessor and R8010 floating point unit
Floating point unit
A floating-point unit is a part of a computer system specially designed to carry out operations on floating point numbers. Typical operations are addition, subtraction, multiplication, division, and square root...
accompanied by a "streaming" cache and its associated controllers. Much of the POWER Challenge's performance depended on the R8000, a microprocessor intended to achieve supercomputing performance and designed for floating-point scientific applications. As a result, the R8000 had features such as fused multiply–add instructions and a large cache.
In 1995, Silicon Graphics upgraded the POWER Challenge with R8000 microprocessors clocked at 90 MHz, enabling the system to scale up to 6.48 GFLOPS, an improvement of 1 GFLOPS over the previous R8000 microprocessor clocked at 75 MHz.
| Model | # of CPUs | CPU | CPU MHz | L2 cache | Memory | Chassis | Introduced | Discontinued |
|---|---|---|---|---|---|---|---|---|
| L (Large) |
1 to 6 | R8000 | 75 or 90 | 4 MB | 6 GB | Deskside | ? | 21 January 1997 |
| GR (Graphics Ready) |
1 to 12 | R8000 | 75 or 90 | 4 MB | ? | ? | ? | 21 January 1997 |
| XL (Extra Large) |
2 or 18 | R8000 | 75 or 90 | 4 MB | 64 MB to 16 GB | Rackmount | ? | 21 January 1997 |
POWER Challenge 10000
The POWER Challenge 10000 referred to POWER Challenge-based systems that used the R10000R10000
The R10000, code-named "T5", is a RISC microprocessor implementation of the MIPS IV instruction set architecture developed by MIPS Technologies, Inc. , then a division of Silicon Graphics, Inc. . The chief designers were Chris Rowen and Kenneth C. Yeager...
microprocessor. These models were introduced in January 1996, succeeding the R4400-based Challenge and the R8000-based POWER Challenge, although such systems co-existed with the POWER Challenge 10000 for some time. To support the new R10000s, a new CPU board, the "IP25" was introduced. The new CPU board, like previous IP19 CPU board, support four processors each and their associated secondary caches.
| Model | # of CPUs | CPU | CPU MHz | L2 cache | Memory | Chassis |
|---|---|---|---|---|---|---|
| XL (Extra Large) |
2, 4, 8, 12, 16, 24 or 36 |
R10000 | 195 | 1 or 2 MB | 64 MB to 16 GB | Rackmount |
CHALLENGEarray
The CHALLENGEarray and POWER CHALLENGEarray is a clusterCluster (computing)
A computer cluster is a group of linked computers, working together closely thus in many respects forming a single computer. The components of a cluster are commonly, but not always, connected to each other through fast local area networks...
of Challenge or POWER Challenge servers respectively. The CHALLENGEarray supports 2 to 288 R10000
R10000
The R10000, code-named "T5", is a RISC microprocessor implementation of the MIPS IV instruction set architecture developed by MIPS Technologies, Inc. , then a division of Silicon Graphics, Inc. . The chief designers were Chris Rowen and Kenneth C. Yeager...
processors while the POWER CHALLENGEarray supports 2 to 144 R8000 processors and up to 128 GB of memory. The POWER CHALLENGEarray was introduced on 15 November 1994.
Other models
Other systems from Silicon Graphics that used the "Challenge" brand were the Challenge M and the Challenge S. These systems were repackaged Silicon Graphics Indigo2 and IndySGI Indy
The Indy, code-named "Guinness", is a low-end workstation introduced on 12 July 1993. Developed and manufactured by Silicon Graphics Incorporated , it was the result of their attempt to obtain a share of the low-end computer-aided design market, which was dominated at the time by other workstation...
workstation
Workstation
A workstation is a high-end microcomputer designed for technical or scientific applications. Intended primarily to be used by one person at a time, they are commonly connected to a local area network and run multi-user operating systems...
s that were not configured with the graphics hardware that made them useful as workstations. These systems were Challenges in name only and have no architectural similarity with the multiprocessing Challenges, although they had cases with the same blue hue as proper Challenges. They were branded as such in order for the systems to be marketed as part of the Challenge server family, positioned as entry level servers.
Description
The deskside enclosure is predominately black with a vertical blue strip on right side. The rackmount enclosure is black, but the front is blue with a horizontal black strip in the middle where the system controller display is mounted. Deskside systems have a width of 54 cm (21 inches), a height of 65 cm (26 inches), a depth of 74 cm (29 inches) and a weighs a minimum of 89 kg (195 lbs). Rackmount systems have a width of 69 cm (27 inches), a height of 159 cm (62.3 inches), a depth of 122 cm (48 inches) and weighs a maximum of 544 kg (1200 lbs).Rackmount systems have a 1,900 watt power supply.
Architecture
The Challenge is a shared-memoryShared memory
In computing, shared memory is memory that may be simultaneously accessed by multiple programs with an intent to provide communication among them or avoid redundant copies. Depending on context, programs may run on a single processor or on multiple separate processors...
multiprocessor
Multiprocessor
Computer system having two or more processing units each sharing main memory and peripherals, in order to simultaneously process programs.Sometimes the term Multiprocessor is confused with the term Multiprocessing....
computer. The system is based on nodes, which are implemented as boards
Printed circuit board
A printed circuit board, or PCB, is used to mechanically support and electrically connect electronic components using conductive pathways, tracks or signal traces etched from copper sheets laminated onto a non-conductive substrate. It is also referred to as printed wiring board or etched wiring...
that plug into a midplane containing Ebus slots and the POWERpath-2 "Ebus" bus, a system bus that the nodes use to communicate with other nodes. The POWERpath-2 bus consists of a 256-bit path for data and a 40-bit path for addressing clocked at 47.6 MHz (21-nanosecond cycle), providing 1.2 GB/s of sustained bandwidth.
The midplane in DM and L models contains five Ebus slots that can support a combination of three CPU, one memory or two POWERchannel-2 interface boards. The midplane also contains five VME
VMEbus
VMEbus is a computer bus standard, originally developed for the Motorola 68000 line of CPUs, but later widely used for many applications and standardized by the IEC as ANSI/IEEE 1014-1987. It is physically based on Eurocard sizes, mechanicals and connectors , but uses its own signalling system,...
expansion slots.
The midplane in XL models contains fifteen Ebus slots that can support a combination of nine CPU, eight memory or five POWERchannel-2 interface boards. The midplane also contains six VME expansion slots and three power board slots.
Boards
The Challenge uses a board set known as the POWERpath-2 board set, code named "Everest". The boards that make up this board set are the IP19, IP21, IP25 CPU boards, the MC3 memory board and the IO4 POWERchannel-2 interface board.CPU boards
The CPU board contains the microprocessors. There are three models of CPU boards, the IP19, IP21 and IP25. The IP19 can be configured with two or four R4400 microprocessors. It also contains five CPU Interface ASICs, four for implementing the data path and one for implementing the address path. These ASICs contain an average of 80,000 gates each. The IP21 supports the R8000 microprocessor and can be configured with one or two such microprocessors. The IP25 supported R10000 microprocessors.MC3
Memory is provided by the MC3 memory board, which contains thirty-two single in-line memory moduleSIMM
A SIMM, or single in-line memory module, is a type of memory module containing random access memory used in computers from the early 1980s to the late 1990s. It differs from a dual in-line memory module , the most predominant form of memory module today, in that the contacts on a SIMM are redundant...
(SIMM) slots and two leaf controllers. Fast page mode (FPM) error correcting code (ECC) SIMMs with capacities of 16 MB (known as the "high-density" SIMM) and 64 MB (known as the "super-density" SIMM) are supported, enables the board to provide 64 MB to 2 GB of memory. The SIMMs are installed in groups of four.
The memory is organized into eight banks, with four banks forming a leaf. The memory can be interleaved if there are two or more leaves present in the system. The memory bus is 576-bit wide, with a 512-bit path for data and a 64-bit path for ECC. The memory is controlled by the two leaf controllers. Each leaf controller manages four banks of memory and half of a memory transaction. It is therefore connected to 256 bits of the memory bus and 128 bits of the POWERpath-2 bus.
Memory transactions are 128-byte wide, the same width as the cache line of the MIPS microprocessors used. A memory read is completed in two cycles of the memory clock, and is buffered by the leaf controllers before it is placed in a sent over the POWERpath-2 bus in four cycles of the POWERpath-2 bus clock.
The SIMMs are protected by ECC, and the ECC implementation can correct single-bit errors and detect double-bit errors. The SIMMs also contain built-in self-test circuitry, which tests the SIMM during power on or reset and alerts the firmware, which disables the bank(s) of memory containing faulty SIMM(s), if faults are detected.