PA-7100LC
Encyclopedia
The PA-7100LC is a microprocessor
that implements the PA-RISC 1.1
instruction set architecture (ISA) developed by Hewlett-Packard
(HP). It is also known as the PCX-L, and by its code-name, Hummingbird. It was designed as a low-cost microprocessor for low-end systems. The first systems to feature the PA-7100LC were introduced in January 1994. These systems used 60 and 80 MHz parts. A 100 MHz part debuted in June 1994. The PA-7100LC was the first PA-RISC microprocessor to implement the MAX-1
multimedia instructions, an early single instruction, multiple data
(SIMD) multimedia instruction set extension that provided instructions for improving the performance of MPEG video decoding.
The PA-7100LC was based on the PA-7100
. Major improvements were improved superscalar
execution and an extra integer unit. The PA-7100LC also implemented architectural improvements including the MAX-1 multimedia instructions, uncacheable memory pages, and bi-endian support. Superscalar execution was improved by adding the extra integer unit and modifying the control logic so that two integer instructions, two load-stores, or an integer and a load-store can be issued in one cycle in addition to the existing instruction combinations supported by the PA-7100.
A number of modifications were made to circuits derived from the PA-7100LC. Prominently, the floating-point unit multiplier was modified to take up less area by halving the tree of carry-save adders that summed the partial products of the mantissa
. This simplification left the latency of single precision multiplies unchanged (two cycles), but increased the latency of double precision multiplies to three cycles. The performance loss was deemed acceptable as the PA-7100LC was designed for mid-range multimedia workstations where single-precision multiplies are more prevalent. Integrated on-die to lower costs is a memory controller
that supports up to 2 GB of memory and an I/O controller.
The organization of the caches are different to that of most HP-designed PA-RISC CPUs. The large external instruction and data caches have been replaced by an on-die instruction cache with a 1 KB capacity and a large external 8 KB to 2 MB cache. The external cache is unified, containing both instructions and data.
The PA-7100LC consists of 900,000 transistors and measures 14.2 by 14.2 mm for an area of 201.64 mm2. It was fabricated by HP in their 0.8 μm three-level metal CMOS26B process. The PA-7100LC is packaged in a 432-pin ceramic pin grid array.
in HP's workstations and servers. The PA-7300LC integrates an improved PA-7100LC, 64 KB instruction and data caches, L2 cache controller, memory controller and a GSC bus
controller onto a single chip. It was the first PA-RISC microprocessor to include any significant amount of on-chip cache. The L2 unified cache was optional and could be protected by parity. It could be built from register-to-register, flow-through or asynchronous SRAM.
The PA-7300LC contained 9.2 million transistors, of which 1.2 million are used in logic and 8 million are used in the caches; and measured 15.3 by 17.0 mm for an area of 260.1 mm2. It was fabricated by HP in their CMOS14C process, a 0.5 µm, 3.3 V, four-layer-metal CMOS process.
Microprocessor
A microprocessor incorporates the functions of a computer's central processing unit on a single integrated circuit, or at most a few integrated circuits. It is a multipurpose, programmable device that accepts digital data as input, processes it according to instructions stored in its memory, and...
that implements the PA-RISC 1.1
PA-RISC
PA-RISC is an instruction set architecture developed by Hewlett-Packard. As the name implies, it is a reduced instruction set computer architecture, where the PA stands for Precision Architecture...
instruction set architecture (ISA) developed by Hewlett-Packard
Hewlett-Packard
Hewlett-Packard Company or HP is an American multinational information technology corporation headquartered in Palo Alto, California, USA that provides products, technologies, softwares, solutions and services to consumers, small- and medium-sized businesses and large enterprises, including...
(HP). It is also known as the PCX-L, and by its code-name, Hummingbird. It was designed as a low-cost microprocessor for low-end systems. The first systems to feature the PA-7100LC were introduced in January 1994. These systems used 60 and 80 MHz parts. A 100 MHz part debuted in June 1994. The PA-7100LC was the first PA-RISC microprocessor to implement the MAX-1
Multimedia Acceleration eXtensions
The Multimedia Acceleration eXtensions or MAX are instruction set extensions to the Hewlett-Packard PA-RISC instruction set architecture ....
multimedia instructions, an early single instruction, multiple data
SIMD
Single instruction, multiple data , is a class of parallel computers in Flynn's taxonomy. It describes computers with multiple processing elements that perform the same operation on multiple data simultaneously...
(SIMD) multimedia instruction set extension that provided instructions for improving the performance of MPEG video decoding.
The PA-7100LC was based on the PA-7100
PA-7100
The PA-7100 is a microprocessor developed by Hewlett-Packard that implemented the PA-RISC 1.1 instruction set architecture . It is also known as the PCX-T and by its code-name Thunderbird. It was introduced in early 1992 and was the first PA-RISC microprocessor to integrate the floating-point unit...
. Major improvements were improved superscalar
Superscalar
A superscalar CPU architecture implements a form of parallelism called instruction level parallelism within a single processor. It therefore allows faster CPU throughput than would otherwise be possible at a given clock rate...
execution and an extra integer unit. The PA-7100LC also implemented architectural improvements including the MAX-1 multimedia instructions, uncacheable memory pages, and bi-endian support. Superscalar execution was improved by adding the extra integer unit and modifying the control logic so that two integer instructions, two load-stores, or an integer and a load-store can be issued in one cycle in addition to the existing instruction combinations supported by the PA-7100.
A number of modifications were made to circuits derived from the PA-7100LC. Prominently, the floating-point unit multiplier was modified to take up less area by halving the tree of carry-save adders that summed the partial products of the mantissa
Mantissa
* The mantissa is the significand in a common logarithm or floating-point number.* Metaphorically, it is the part of the self that eludes conscious awareness or self-understanding.* An addition of little importance.Mantissa may also refer to:...
. This simplification left the latency of single precision multiplies unchanged (two cycles), but increased the latency of double precision multiplies to three cycles. The performance loss was deemed acceptable as the PA-7100LC was designed for mid-range multimedia workstations where single-precision multiplies are more prevalent. Integrated on-die to lower costs is a memory controller
Memory controller
The memory controller is a digital circuit which manages the flow of data going to and from the main memory. It can be a separate chip or integrated into another chip, such as on the die of a microprocessor...
that supports up to 2 GB of memory and an I/O controller.
The organization of the caches are different to that of most HP-designed PA-RISC CPUs. The large external instruction and data caches have been replaced by an on-die instruction cache with a 1 KB capacity and a large external 8 KB to 2 MB cache. The external cache is unified, containing both instructions and data.
The PA-7100LC consists of 900,000 transistors and measures 14.2 by 14.2 mm for an area of 201.64 mm2. It was fabricated by HP in their 0.8 μm three-level metal CMOS26B process. The PA-7100LC is packaged in a 432-pin ceramic pin grid array.
PA-7300LC
The PA-7300LC was a further development of the PA-7100LC. It was introduced in mid-1996 as a low-end to mid-range microprocessor complementing the high-end PA-8000PA-8000
The PA-8000 , code-named Onyx, is a microprocessor developed and fabricated by Hewlett-Packard that implemented the PA-RISC 2.0 instruction set architecture . It was a completely new design with no circuitry derived from previous PA-RISC microprocessors...
in HP's workstations and servers. The PA-7300LC integrates an improved PA-7100LC, 64 KB instruction and data caches, L2 cache controller, memory controller and a GSC bus
GSC bus
GSC is a bus used in many of the HP 9000 workstations and servers. The acronym has various explanations, including Gecko System Connect , Gonzo System Connect and General System Connect....
controller onto a single chip. It was the first PA-RISC microprocessor to include any significant amount of on-chip cache. The L2 unified cache was optional and could be protected by parity. It could be built from register-to-register, flow-through or asynchronous SRAM.
The PA-7300LC contained 9.2 million transistors, of which 1.2 million are used in logic and 8 million are used in the caches; and measured 15.3 by 17.0 mm for an area of 260.1 mm2. It was fabricated by HP in their CMOS14C process, a 0.5 µm, 3.3 V, four-layer-metal CMOS process.