Multi Project Chip
Encyclopedia
Multi-Project Chip or Multi-Project Wafer (MPW) services integrate onto microelectronics
wafers a number of different integrated circuit
designs from various teams including designs from private firms, students and researchers from universities. Because IC fabrication costs are extremely high, it makes sense to share mask and wafer resources to produce designs in low quantities. Worldwide, several MPW services are available from government-supported institutions or from private firms including MOSIS, CMP and Europractice.
The first well known MPW service was MOSIS
(Metal Oxide Silicon Implementation Service), established by DARPA as a technical and human infrastructure for VLSI. MOSIS began in 1981 after Lynn Conway
organized the first VLSI System Design Course at M.I.T. in 1978.
MOSIS primarily services commercial users now but continues to serve university students and researchers.
With MOSIS, designs are submitted for fabrication using either open (i. e., non-proprietary) VLSI layout design rules
or vendor proprietary rules.
Designs are pooled into common lots and run through the fabrication process at foundries. The completed chips (packaged or unpackaged) are returned to customers.
Many silicon fabrication facilities offer MPW runs or a company can produce its own MPW, e.g. combine several of its own designs to form one wafer completely owned by the company. In the latter case, it may be profitable to use most of the wafer for production chips and a small portion for producing prototypes of next generation chips.
Microelectronics
Microelectronics is a subfield of electronics. As the name suggests, microelectronics relates to the study and manufacture of very small electronic components. Usually, but not always, this means micrometre-scale or smaller,. These devices are made from semiconductors...
wafers a number of different integrated circuit
Integrated circuit
An integrated circuit or monolithic integrated circuit is an electronic circuit manufactured by the patterned diffusion of trace elements into the surface of a thin substrate of semiconductor material...
designs from various teams including designs from private firms, students and researchers from universities. Because IC fabrication costs are extremely high, it makes sense to share mask and wafer resources to produce designs in low quantities. Worldwide, several MPW services are available from government-supported institutions or from private firms including MOSIS, CMP and Europractice.
The first well known MPW service was MOSIS
MOSIS
MOSIS is probably the oldest integrated circuit foundry service and one of the first Internet services other than supercomputing services and basic infrastructure such as E-mail or FTP....
(Metal Oxide Silicon Implementation Service), established by DARPA as a technical and human infrastructure for VLSI. MOSIS began in 1981 after Lynn Conway
Lynn Conway
Lynn Conway is an American computer scientist, electrical engineer, inventor, trans woman, and activist for the transgender community....
organized the first VLSI System Design Course at M.I.T. in 1978.
MOSIS primarily services commercial users now but continues to serve university students and researchers.
With MOSIS, designs are submitted for fabrication using either open (i. e., non-proprietary) VLSI layout design rules
Design rule checking
Design Rule Checking or Check is the area of Electronic Design Automation that determines whether the physical layout of a particular chip layout satisfies a series of recommended parameters called Design Rules...
or vendor proprietary rules.
Designs are pooled into common lots and run through the fabrication process at foundries. The completed chips (packaged or unpackaged) are returned to customers.
Many silicon fabrication facilities offer MPW runs or a company can produce its own MPW, e.g. combine several of its own designs to form one wafer completely owned by the company. In the latter case, it may be profitable to use most of the wafer for production chips and a small portion for producing prototypes of next generation chips.