Intel Xeon chipsets
Encyclopedia
Around the time that the Pentium 3 processor was introduced, Intel's Xeon
line diverged from its line of desktop processors, which at the time was using the Pentium branding.
The divergence was implemented by using different sockets; since then, the sockets for Xeon chips have tended to remain constant across several generations of implementation.
The chipsets contain a 'memory controller hub' and an 'I/O controller hub', which tend to be called 'north bridge' and 'south bridge' respectively. The memory controller hub connects to the processors, memory, high-speed I/O such as PCI Express, and to the I/O controller hub by a proprietary link. The I/O controller hub on the other hand, connects to lower-speed I/O, such as hard discs, PCI slots, USB and Ethernet.
Dual processor P6
Intel's initial preferred chipset for Pentium III Xeon was the 840.
Four processor P6
The Pentium III Xeon bus protocol allowed four processors on the same bus, so the 440GX AGPset could be used in four-CPU systems; the limit of 2GB of main memory remained. These support Slot 2
.
There was also the 450NX PCIset, which consisted of several chips: a single 82451NX Memory and IO Bridge Controller roughly analogous to the North Bridge, up to two 82454NX PCI Expander Bridges which converted the protocol used by 451NX to two 32-bit PCI33 or one 64-bit PCI33 bus, along with up to two memory cards each equipped with one 82452NX RAS/CAS Generator chip and two 82453NX Data Path Multiplexer chips. It supported PIIX3 and PIIX4E south bridges, and EDO DRAM.
. It supported up to 8 Pentium III Xeon processors on two busses and maintained cache coherency between them.
.
Note that the 82870P2 chips mentioned above were initially designed for the Intel 870 chipset for Itanium 2, and that the summary page of the E7320 datasheet incorrectly claims three PCI Express interfaces.
' design, in which each socket has its own connection to the chipset. These support LGA 771
.
interfaces; the 5520 is more intended for graphical workstations and the 5500 for servers that do not need vast amounts of PCI Express connectivity
Single processor Sandy Bridge
The Intel C200 series chipsets support the Intel Xeon E3-1200 CPU family.
http://www.intel.com/content/www/us/en/chipsets/6-chipset-c200-chipset-datasheet.html
Xeon
The Xeon is a brand of multiprocessing- or multi-socket-capable x86 microprocessors from Intel Corporation targeted at the non-consumer server, workstation and embedded system markets.-Overview:...
line diverged from its line of desktop processors, which at the time was using the Pentium branding.
The divergence was implemented by using different sockets; since then, the sockets for Xeon chips have tended to remain constant across several generations of implementation.
The chipsets contain a 'memory controller hub' and an 'I/O controller hub', which tend to be called 'north bridge' and 'south bridge' respectively. The memory controller hub connects to the processors, memory, high-speed I/O such as PCI Express, and to the I/O controller hub by a proprietary link. The I/O controller hub on the other hand, connects to lower-speed I/O, such as hard discs, PCI slots, USB and Ethernet.
Dual processor P6P6 (microarchitecture)The P6 microarchitecture is the sixth generation Intel x86 microarchitecture, implemented by the Pentium Pro microprocessor that was introduced in November 1995. It is sometimes referred to as i686. It was succeeded by the NetBurst microarchitecture in 2000, but eventually revived in the Pentium M...
-based Xeon chipsets
Intel's initial preferred chipset for Pentium III Xeon was the 840.| Product name | Codename | Processor FSB supported | Memory type supported | High-speed interfaces provided | Preferred IOCH |
|---|---|---|---|---|---|
| 440GX AGPset | Marlinespike | 100 | One 72-bit-wide channel of SDRAM, with ECC; up to four DIMMs | PIIX4E | |
| 840 | Carmel | 100 or 133 | Two channels RDRAM, two RIMMs per channel |
Four processor P6P6 (microarchitecture)The P6 microarchitecture is the sixth generation Intel x86 microarchitecture, implemented by the Pentium Pro microprocessor that was introduced in November 1995. It is sometimes referred to as i686. It was succeeded by the NetBurst microarchitecture in 2000, but eventually revived in the Pentium M...
-based Xeon chipsets
The Pentium III Xeon bus protocol allowed four processors on the same bus, so the 440GX AGPset could be used in four-CPU systems; the limit of 2GB of main memory remained. These support Slot 2Slot 2
Slot 2 refers to the physical and electrical specification for the 330-lead Single Edge Contact Cartridge used by some of Intel's Pentium II Xeon and certain models of the Pentium III Xeon....
.
There was also the 450NX PCIset, which consisted of several chips: a single 82451NX Memory and IO Bridge Controller roughly analogous to the North Bridge, up to two 82454NX PCI Expander Bridges which converted the protocol used by 451NX to two 32-bit PCI33 or one 64-bit PCI33 bus, along with up to two memory cards each equipped with one 82452NX RAS/CAS Generator chip and two 82453NX Data Path Multiplexer chips. It supported PIIX3 and PIIX4E south bridges, and EDO DRAM.
Eight processor P6-based Xeon chipset
In August 1999 Intel began shipping the Profusion PCIset. The chipset was based on technology developed by CorollaryCorollary
A corollary is a statement that follows readily from a previous statement.In mathematics a corollary typically follows a theorem. The use of the term corollary, rather than proposition or theorem, is intrinsically subjective...
. It supported up to 8 Pentium III Xeon processors on two busses and maintained cache coherency between them.
Dual processor NetBurst-based Xeon chipsets
E7500 corresponded to the first Northwood-based Pentium4 Xeons, E7501 is essentially identical but supports faster FSB and memory. The E7320, E7520 and E7525 chipsets correspond to Prescott-based Pentium4 Xeons, and differ mainly in their PCI Express support. These support Socket 604Socket 604
Socket 604 is a 604 pin microprocessor socket designed to interface an Intel's Xeon processor to the rest of the computer. It provides both an electrical interface as well as physical support. This socket is designed to support a heatsink....
.
| Product name | Codename | Processor FSB supported | Memory type supported | High-speed interfaces provided | Preferred IOCH |
|---|---|---|---|---|---|
| E7205 | Granite Bay | 400 or 533 MHz | Two channels of DDR at 100 MHz or 133 MHz | AGP 8× port, single 32-bit 33 MHz PCI bus, 266 MHz 8-bit hub interface for ICH4 | ICH4 |
| E7320 | Lindenhurst VS | 800 MHz | Two channels of ECC DDR SDRAM at 200 MHz (6.4GB/s peak) | One ×8 PCI Express interface with max theoretical bandwidth of 4 GB/s, which may be configured as two ×4 PCIe interfaces. A 6700PXH provides PCI-X 32-bit and/or 64-bit interfaces at 33 MHz, 66 MHz, 100 MHz, and 133 MHz. | 6300ESB, or 82801ER (ICH5R) |
| E7500 | Plumas | 400 MHz | Two channels of ECC DDR SDRAM at 100 MHz (3.2GB/s peak) | Three ECC 1GB/s (66 MHz ×8, 16-bit) 'Hub Interface' channels, which connect to 82870P2 chips to provide two 64-bit 66 MHz PCI or PCI-X buses each, plus one ECC 533MB/s (66 MHz ×4) connector for ICH3-S | ICH3-S |
| E7501 | Plumas | 533 MHz | Two channels of ECC DDR SDRAM at 133 MHz (4.2GB/s peak) | Three ECC 1GB/s (66 MHz ×8, 16-bit) 'Hub Interface' channels, which connect to 82870P2 chips to provide two 64-bit 66 MHz PCI or PCI-X buses each, plus one ECC 533MB/s (66 MHz ×4) connector for ICH3-S | ICH3-S |
| E7505 | Placer | 533 MHz | Two channels of ECC DDR SDRAM at 133 MHz (4.2GB/s peak) | AGP 8× port, three ECC 1GB/s (66 MHz ×8, 16-bit) 'Hub Interface' channels, which connect to 82870P2 chips to provide two 64-bit 66 MHz PCI or PCI-X buses each, plus one ECC 533MB/s (66 MHz ×4) connector for ICH4 | ICH4 |
| E7520 | Lindenhurst | 800 MHz | Two channels of ECC DDR SDRAM at 200 MHz (6.4GB/s peak) | Three ×8 PCI Express interfaces each with max theoretical bandwidth of 4 GB/s, which may be configured as two ×4 PCIe interfaces. A 6700PXH provides PCI-X 32-bit and/or 64-bit interfaces at 33 MHz, 66 MHz, 100 MHz, and 133 MHz. | 6300ESB, or 82801ER (ICH5R) |
| E7525 | Tumwater | 800 MHz | Two channels of registered DDR333 or DDR2/400 SDRAM | One ×16 and one ×8 PCI Express interface. A 6700PXH can be attached. | 6300ESB, or 82801ER (ICH5R) |
Note that the 82870P2 chips mentioned above were initially designed for the Intel 870 chipset for Itanium 2, and that the summary page of the E7320 datasheet incorrectly claims three PCI Express interfaces.
Quad processor NetBurst-based Xeon chipsets
| Product name | Codename | Processor FSB supported | Memory type supported | High-speed interfaces provided | Preferred IOCH |
|---|---|---|---|---|---|
| E8500 | Twin Castle | 667 MHz | DDR-266, DDR-333 or DDR2-400 | three ×8 and one ×4 PCI Express interface | 82801EB (ICH5), or 82801ER (ICH5R) |
| E8501 | Twin Castle | 667 and 800 MHz | DDR2-400 | 82801EB (ICH5), or 82801ER (ICH5R) |
Single processor Core-based Xeon chipsets
| Product name | Codename | Processor FSB supported | Memory type supported | High-speed interfaces provided | Preferred IOCH |
|---|---|---|---|---|---|
| 3000 | Mukilteo | 533 or 800 or 1066 MHz | Two channels of ECC DDR2-533 or DDR2-667 | PCI Express ×8 port, single 32-bit 33 MHz PCI bus, DMI for ICH7 | ICH7 |
| 3010 | Mukilteo 2 | 533 or 800 or 1066 MHz | Two channels of ECC DDR2-533 or DDR2-667 | PCI Express 1 ×16 or 2 ×8 ports, single 32-bit 33 MHz PCI bus, DMI for ICH7 | ICH7 |
| 3200 | Bigby | 800 or 1066 or 1333 MHz | Two channels of ECC DDR2-667 or DDR2-800 | PCI Express ×8 port, single 32-bit 33 MHz PCI bus, DMI for ICH9 | ICH9 |
| 3210 | Bigby | 800 or 1066 or 1333 MHz | Two channels of ECC DDR2-667 or DDR2-800 | PCI Express 1 ×16 or 2 ×8 ports, single 32-bit 33 MHz PCI bus, DMI for ICH9 | ICH9 |
Dual processor Core-based Xeon chipsets
These chipsets use a 'dual independent busDual independent bus
Dual Independent Bus is a processor architecture that includes two buses: one to the main system memory and another to the level 2 cache...
' design, in which each socket has its own connection to the chipset. These support LGA 771
LGA 771
LGA 771, also known as Socket J, is a CPU interface introduced by Intel in 2006. It is used in Intel Core microarchitecture based DP-capable server processors, the Dual-Core Xeon is codenamed Dempsey, Woodcrest, and Wolfdale and the Quad-Core processors Clovertown, Harpertown...
.
| Product name | Codename | Processor FSB supported | Memory type supported | High-speed interfaces provided | Preferred IOCH |
|---|---|---|---|---|---|
| 5000P | Blackford | 1066, 1333 | Four channels of FB-DIMM at 533 or 667 MHz | Two PCIe ×8 ports, plus two ×4 ports for communication with IOCH | 631xESB or 632xESB |
| 5000V | Blackford | 1066, 1333 | Two channels of FB-DIMM at 533 or 667 MHz | No PCI-e ports are exposed - connection is exclusively to the IOCH | 631xESB or 632xESB |
| 5000Z | Blackford | 1066, 1333 | Two channels of FB-DIMM at 533 or 667 MHz | One PCI-e ×8 port, plus two ×4 ports for communication with IOCH | 631xESB or 632xESB |
| 5000X | Greencreek | 1066, 1333 (has a snoop filter, comprising about 1MB of SRAM, to keep cache coherency traffic between the two sockets from appearing on the external bus) | Four channels of FB-DIMM at 533 or 667 MHz | One PCI-e ×16 port | 631xESB or 632xESB |
| 5100 | San Clemente | 1066, 1333 | Two channels of registered ECC DDR2 | 6 PCIe ×4 ports | 631xESB or 632xESB |
| 5400 | Seaburg | 1066, 1333, 1600; has a more advanced snoop filter than 5000X, comprising about 1.6MB of SRAM | Four channels of FB-DIMM at 533, 667 or 800 MHz | 9 PCIe ×4 ports | 631xESB or 632xESB |
Four processor Core-based Xeon chipsets
This chipset uses four independent buses, and is used by the Tigerton and Dunnington processors.| Launch name | Codename | FSB speed | Memory speed | Fast I/O | IOCH |
|---|---|---|---|---|---|
| 7300 | Clarksboro | 1066. Very sophisticated snoop filter, comprising 4.5MB of SRAM. | Four channels of FB-DIMM at 533 or 667 MHz | 7 PCIe ×4 ports, of which two are usually used to connect to the IOCH | 631x or 632x |
Single processor Nehalem-based Xeon chipsets
The 3450 chipset is also compatible with an Intel Core i5 or Intel Core i3 processor.| Product name | Codename | DMI | Fast I/O | Other features |
|---|---|---|---|---|
| 3400 | Ibex Peak | 1.0, 100 MHz | PCI Express 6 ×1 ports, single 32-bit 33 MHz PCI bus, DMI for processor | 8× USB 2.0, 4× SATA, Integrated LAN |
| 3420 | Ibex Peak | 1.0, 100 MHz | PCI Express 8 ×1 ports, single 32-bit 33 MHz PCI bus, DMI for processor | 12× USB 2.0, 6× SATA, Integrated LAN |
| 3450 | Ibex Peak | 1.0, 100 MHz | PCI Express 8 ×1 ports, single 32-bit 33 MHz PCI bus, DMI for processor | 14× USB 2.0, 6× SATA, Integrated LAN |
Dual processor Nehalem-based Xeon chipsets
The Nehalem-based Xeons for dual-socket systems, initially launched as the Xeon 55xx series, feature a very different system structure: the memory controllers are on the CPU, and the CPUs can communicate with one another as peers without going via the chipset. This means that the 5500 and 5520 chipsets are essentially QPI to PCI ExpressPCI Express
PCI Express , officially abbreviated as PCIe, is a computer expansion card standard designed to replace the older PCI, PCI-X, and AGP bus standards...
interfaces; the 5520 is more intended for graphical workstations and the 5500 for servers that do not need vast amounts of PCI Express connectivity
| Launch name | Codename | QPI ports | QPI speed | Fast I/O | IOCH | Other features |
|---|---|---|---|---|---|---|
| 5500 | Tylersburg-24D | 2 | 4.8, 5.86 or 6.4 GT/s | 1 ×16 PCIe Gen 2, 2 ×4 PCIe Gen 1 to talk to southbridge | ICH10 (ICH9 also possible) | Integrated Management Engine with its own 100 Mbit Ethernet |
| 5520 | Tylersburg-36D | 2 | 4.8, 5.86 or 6.4 GT/s | 2 ×16 PCIe Gen 2, 1 ×4 PCIe Gen 1 to talk to southbridge | ICH10 (ICH9 also possible) | Integrated Management Engine with its own 100 Mbit Ethernet |
Four processor Nehalem-based Xeon chipsets
| Launch name | Codename | QPI ports | QPI speed | Fast I/O | IOCH | Other features |
|---|---|---|---|---|---|---|
| 7500 | Boxboro | 4 | 6.4 GT/s | 2 ×16 PCIe Gen 2, 1 ×4 PCIe Gen 1 to talk to southbridge | ICH10 (ICH9 also possible) | Integrated Management Engine with its own 100 Mbit Ethernet |
Single processor Sandy BridgeSandy Bridge (microarchitecture)Sandy Bridge is the codename for a microarchitecture developed by Intel beginning in 2005 for central processing units in computers to replace the Nehalem microarchitecture...
-based Xeon chipsets
The Intel C200 series chipsets support the Intel Xeon E3-1200 CPU family.| Product name | Codename | DMI | Fast I/O | Other features |
|---|---|---|---|---|
| C202 | Cougar Point | 2.0, 100 MHz | PCI Express 8 × 1 ports, single 32-bit 33 MHz PCI bus, DMI for processor | 12 × USB 2.0, 6 × SATA 1.5/3 Gbit/s, Integrated LAN |
| C204 | Cougar Point | 2.0, 100 MHz | PCI Express 8 × 1 ports, single 32-bit 33 MHz PCI bus, DMI for processor | 12 × USB 2.0, 2 x SATA 1.5/3/6 Gbit/s + 4 × SATA 1.5/3 Gbit/s, Integrated LAN |
| C206 | Cougar Point | 2.0, 100 MHz | PCI Express 8 × 1 ports, single 32-bit 33 MHz PCI bus, DMI for processor | 14 × USB 2.0, 2 x SATA 1.5/3/6 Gbit/s + 4 × SATA 1.5/3 Gbit/s, Integrated LAN, Integrated Graphics, Intel Anti-Theft Technology, Active Management Technology 7.0 |