Engineering Change Order
Encyclopedia
Engineering Change Orders (ECO) are used for changes in components, assemblies, or documents such as processes and work instructions. They may also be used for changes in specifications.
ECOs are also called an Engineering Change Note or Engineering Change Notice
(ECN) or just engineering change (EC).
In a typical system development cycle, the specification or the implementation is likely to change during engineering development or during integration of the system elements. These last-minute design changes are commonly referred to as engineering change orders (ECOs) and affect the functionality of a design after it has been wholly or partially completed. ECOs can compensate for design errors found during debug or changes that are made to the design specification to compensate for design problems in other areas of the system design.
logic synthesis
, Technology Mapping, place
, route
, layout extraction
, and timing verification
. EDA tools are often built with incremental modes of operation to facilitate this type of ECO.
After masks have been made, ECOs may be done to save money. If a change can be implemented by modifying only a few of the layers (typically metal) then the cost is much less than it would be if the design was re-built from scratch. This is because starting the process from the beginning will almost always require new photomask
s for all layers, and each of the 20 or so masks in a modern semiconductor fabrication
process is quite expensive. A change implemented by modifying only a few layers is typically called a metal-mask ECO or a post-mask ECO. Designers often sprinkle a design with unused logic gates, and EDA tools have specialized commands, to make this process easier.
One of the most common ECOs in ASIC design is the Gate-level netlist ECO. In this flow, engineers manually (and often tediously) hand-edit the gate level netlist, instead of re-running logic synthesis. The netlist files have to be searched for the logic affected by the change, the files need to be edited to implement the changes up and down the hierarchy, and the changes need to be tracked and verified to make sure exactly what needs to change gets changed and nothing more. This is a very time and resource intensive process that is easily subject to errors. Therefore formal equivalence checking
is normally used after ECOs to ensure the revised implementation matches the revised specification.
With Time to market
pressures and rising mask costs in the semiconductor industry
, several EDA
companies are beginning to bring more automation into the ECO implementation process. Most popular place
& route
products have some level of built-in ECO Routing to help with implementing physical-level ECOs. Cadence Design Systems
has recently announced a product called Conformal ECO Designer, that automates the creation of Functional ECOs, usually the most tedious process in implementing an ECO. It uses formal equivalence checking
and Logic synthesis
techniques to produce a Gate-Level ECO netlist based on the changed RTL. Synopsys
in the past had a product called ECO Compiler that is now defunct.
An ECN must contain at least this information:
ECOs are also called an Engineering Change Note or Engineering Change Notice
Engineering Change Notice
An Engineering Change Notice , or Change Notice, is a document which records or authorises a change to a design. The reasons for the change should also be recorded....
(ECN) or just engineering change (EC).
In a typical system development cycle, the specification or the implementation is likely to change during engineering development or during integration of the system elements. These last-minute design changes are commonly referred to as engineering change orders (ECOs) and affect the functionality of a design after it has been wholly or partially completed. ECOs can compensate for design errors found during debug or changes that are made to the design specification to compensate for design problems in other areas of the system design.
Chip design
In chip design, ECO is the process of inserting a logic change directly into the netlist after it has already been processed by an automatic tool. Before the chip masks are made, ECOs are usually done to save time, by avoiding the need for full ASICASIC
ASIC may refer to:* Application-specific integrated circuit, an integrated circuit developed for a particular use, as opposed to a customised general-purpose device.* ASIC programming language, a dialect of BASIC...
logic synthesis
Logic synthesis
In electronics, logic synthesis is a process by which an abstract form of desired circuit behavior, typically register transfer level , is turned into a design implementation in terms of logic gates. Common examples of this process include synthesis of HDLs, including VHDL and Verilog...
, Technology Mapping, place
Placement (EDA)
Placement is an essential step in electronic design automation - the portion of the physical design flow that assigns exact locations for various circuitcomponents within the chip’s core area...
, route
Routing (EDA)
In electronic design, wire routing, commonly called simply routing, is a step in the design of printed circuit boards and integrated circuits . It builds on a preceding step, called placement, which determines the location of each active element of an IC or component on a PCB...
, layout extraction
Layout extraction
The electric circuit extraction or simply circuit extraction, also netlist extraction, is the translation of an integrated circuit layout back into the electrical circuit it is intendedto represent...
, and timing verification
Static timing analysis
Static Timing Analysis is a method of computing the expected timing of a digital circuit without requiring simulation.High-performance integrated circuits have traditionally been characterized by the clock frequency at which they operate...
. EDA tools are often built with incremental modes of operation to facilitate this type of ECO.
After masks have been made, ECOs may be done to save money. If a change can be implemented by modifying only a few of the layers (typically metal) then the cost is much less than it would be if the design was re-built from scratch. This is because starting the process from the beginning will almost always require new photomask
Photomask
A photomask is an opaque plate with holes or transparencies that allow light to shine through in a defined pattern. They are commonly used in photolithography.-Overview:...
s for all layers, and each of the 20 or so masks in a modern semiconductor fabrication
Semiconductor fabrication
Semiconductor device fabrication is the process used to create the integrated circuits that are present in everyday electrical and electronic devices. It is a multiple-step sequence of photolithographic and chemical processing steps during which electronic circuits are gradually created on a wafer...
process is quite expensive. A change implemented by modifying only a few layers is typically called a metal-mask ECO or a post-mask ECO. Designers often sprinkle a design with unused logic gates, and EDA tools have specialized commands, to make this process easier.
One of the most common ECOs in ASIC design is the Gate-level netlist ECO. In this flow, engineers manually (and often tediously) hand-edit the gate level netlist, instead of re-running logic synthesis. The netlist files have to be searched for the logic affected by the change, the files need to be edited to implement the changes up and down the hierarchy, and the changes need to be tracked and verified to make sure exactly what needs to change gets changed and nothing more. This is a very time and resource intensive process that is easily subject to errors. Therefore formal equivalence checking
Formal equivalence checking
Formal equivalence checking process is a part of electronic design automation , commonly used during the development of digital integrated circuits, to formally prove that two representations of a circuit design exhibit exactly the same behavior....
is normally used after ECOs to ensure the revised implementation matches the revised specification.
With Time to market
Time to market
In commerce, time to market is the length of time it takes from a product being conceived until its being available for sale. TTM is important in industries where products are outmoded quickly...
pressures and rising mask costs in the semiconductor industry
Semiconductor industry
The semiconductor industry is the aggregate collection of companies engaged in the design and fabrication of semiconductor devices. It formed around 1960, once the fabrication of semiconductors became a viable business...
, several EDA
Electronic design automation
Electronic design automation is a category of software tools for designing electronic systems such as printed circuit boards and integrated circuits...
companies are beginning to bring more automation into the ECO implementation process. Most popular place
Placement (EDA)
Placement is an essential step in electronic design automation - the portion of the physical design flow that assigns exact locations for various circuitcomponents within the chip’s core area...
& route
Routing (EDA)
In electronic design, wire routing, commonly called simply routing, is a step in the design of printed circuit boards and integrated circuits . It builds on a preceding step, called placement, which determines the location of each active element of an IC or component on a PCB...
products have some level of built-in ECO Routing to help with implementing physical-level ECOs. Cadence Design Systems
Cadence Design Systems
Cadence Design Systems, Inc is an electronic design automation software and engineering services company, founded in 1988 by the merger of SDA Systems and ECAD, Inc...
has recently announced a product called Conformal ECO Designer, that automates the creation of Functional ECOs, usually the most tedious process in implementing an ECO. It uses formal equivalence checking
Formal equivalence checking
Formal equivalence checking process is a part of electronic design automation , commonly used during the development of digital integrated circuits, to formally prove that two representations of a circuit design exhibit exactly the same behavior....
and Logic synthesis
Logic synthesis
In electronics, logic synthesis is a process by which an abstract form of desired circuit behavior, typically register transfer level , is turned into a design implementation in terms of logic gates. Common examples of this process include synthesis of HDLs, including VHDL and Verilog...
techniques to produce a Gate-Level ECO netlist based on the changed RTL. Synopsys
Synopsys
Synopsys, Inc. is one of the largest companies in the Electronic Design Automation industry. Synopsys' first and best-known product is Design Compiler, a logic-synthesis tool. Synopsys offers a wide range of other products used in the design of an application-specific integrated circuit...
in the past had a product called ECO Compiler that is now defunct.
Product design
In product development the need for change is caused by:- Correction of a design error that doesn’t become evident until testing and modeling, or customer use reveals it.
- A change in the customers’ requirements necessitating the redesign of part of the product
- A change in material or manufacturing method. This can be caused by a lack of material availability, a change in vendor, or to compensate for a design error.
An ECN must contain at least this information:
- Identification of what needs to be changed. This should include the part number and name of the component and reference to the drawings that show the component in detail or assembly.
- Reason(s) for the change.
- Description of the change. This includes a drawing of the component before and after the change. Generally, these drawings are only of the detail affected by the change.
- List of documents and departments affected by the change. The most important part of making a change is to see that all pertinent groups are notified and all documents updated.
- Approval of the change. As with the detail and assembly drawings, the changes must be approved by management.
- Instruction about when to introduce the change—immediately (scrapping current inventory), during the next production run, or at some other milestone.