Cycle Accurate Simulator
Encyclopedia
A Cycle Accurate Simulator (CAS) is a computer program that simulates a microarchitecture
cycle-accurate. In contrast an instruction set simulator
simulates an Instruction Set Architecture usually faster but not cycle-accurate to a specific implementation of this architecture. They are often used when emulating older hardware, where time precisions is very important from legacy reasons. More often CAS is used when designing new microprocessors - they can be tested, and benchmarked accurately (including running full operating system, or compilers) without actually building physical chip, and easily change design many times to meet expected plan.
Cycle Accurate Simulator, must ensure that all operations are executed in the proper virtual (or real if it is possible) time - branch prediction, cache misses, fetches, pipeline stalls, thread context switching, and many other subtle aspects of microprocessors.
Microarchitecture
In computer engineering, microarchitecture , also called computer organization, is the way a given instruction set architecture is implemented on a processor. A given ISA may be implemented with different microarchitectures. Implementations might vary due to different goals of a given design or...
cycle-accurate. In contrast an instruction set simulator
Instruction Set Simulator
An instruction set simulator is a simulation model, usually coded in a high-level programming language, which mimics the behavior of a mainframe or microprocessor by "reading" instructions and maintaining internal variables which represent the processor's registers.Instruction simulation is a...
simulates an Instruction Set Architecture usually faster but not cycle-accurate to a specific implementation of this architecture. They are often used when emulating older hardware, where time precisions is very important from legacy reasons. More often CAS is used when designing new microprocessors - they can be tested, and benchmarked accurately (including running full operating system, or compilers) without actually building physical chip, and easily change design many times to meet expected plan.
Cycle Accurate Simulator, must ensure that all operations are executed in the proper virtual (or real if it is possible) time - branch prediction, cache misses, fetches, pipeline stalls, thread context switching, and many other subtle aspects of microprocessors.