BEOL
Encyclopedia
Back-end-of-line denotes the second portion of IC fabrication where the individual devices (transistors, capacitors, resistors, etc.) get interconnected with wiring on the wafer. BEOL generally begins when the first layer of metal is deposited on the wafer. It includes contacts, insulating layers (dielectric
s), metal levels, and bonding sites for chip-to-package connections.
After a FEOL step there is a wafer with isolated transistors (without any wires). In BEOL part of fabrication stage contacts (pads), interconnect wires, vias and dielectric structures are formed. For modern IC process, more than 10 metal layers can be added in the BEOL.
The process used to form DRAM capacitors creates a rough and hilly surface, which makes it difficult to add metal interconnect layers and still maintain good yield.
In 1998, state-of-the-art DRAM processes had 4 metal layers, while state-of-the-art logic processes had 7 metal layers.
As of 2002, 5 or 6 layers of metal interconnect are common.
As of 2009, typical DRAM devices (1 Gbit) use 3 layers of metal interconnect, tungsten on the first layer and aluminum on the higher layers.
As of 2011, many gate arrays are available with a 3-layer interconnect.
Many power ICs and analog ICs use a 3-layer interconnect.
The top-most layers of a chip have the thickest and widest and most widely-separated metal layers, which make the wires on those layers have the least resistance and smallest RC time delay, so they are used for power distribution and clock distribution.
The bottom-most metal layers of the chip, closest to the transistors, have thin, narrow, tightly-packed wires, used only for local interconnect.
Adding layers can potentially improve performance, but adding layers also reduces yield and increases manufacturing cost.
The AMD Athlon Thunderbird has 6 interconnect layers,
the AMD Athlon Palomino has 7 interconnect layers,
the AMD Athlon Thoroughbred A has 8 interconnect layers,
and the AMD Athlon Thoroughbred B has 9 interconnect layers.
The Intel Xeon Dunnington has nine copper interconnect layers.
Steps of the BEOL:
Before 1998, practically all chips used aluminum for the metal interconnection layers.
The four metals with the highest electrical conductivity are silver with the highest conductivity, then copper, then gold, then aluminum.
As of 2011, many commercial processes support 2 or 3 metal layers; the most layers supported on a commercial process is 11 layers, and 12 layers are expected to be supported soon.
After BEOL there is a "Backend process" (also called post-fab), which is done not in the cleanroom, often by different company.
It includes wafer test
, wafer backgrinding
, die separation
, die tests, IC packaging
and final test.
Dielectric
A dielectric is an electrical insulator that can be polarized by an applied electric field. When a dielectric is placed in an electric field, electric charges do not flow through the material, as in a conductor, but only slightly shift from their average equilibrium positions causing dielectric...
s), metal levels, and bonding sites for chip-to-package connections.
After a FEOL step there is a wafer with isolated transistors (without any wires). In BEOL part of fabrication stage contacts (pads), interconnect wires, vias and dielectric structures are formed. For modern IC process, more than 10 metal layers can be added in the BEOL.
The process used to form DRAM capacitors creates a rough and hilly surface, which makes it difficult to add metal interconnect layers and still maintain good yield.
In 1998, state-of-the-art DRAM processes had 4 metal layers, while state-of-the-art logic processes had 7 metal layers.
As of 2002, 5 or 6 layers of metal interconnect are common.
As of 2009, typical DRAM devices (1 Gbit) use 3 layers of metal interconnect, tungsten on the first layer and aluminum on the higher layers.
As of 2011, many gate arrays are available with a 3-layer interconnect.
Many power ICs and analog ICs use a 3-layer interconnect.
The top-most layers of a chip have the thickest and widest and most widely-separated metal layers, which make the wires on those layers have the least resistance and smallest RC time delay, so they are used for power distribution and clock distribution.
The bottom-most metal layers of the chip, closest to the transistors, have thin, narrow, tightly-packed wires, used only for local interconnect.
Adding layers can potentially improve performance, but adding layers also reduces yield and increases manufacturing cost.
The AMD Athlon Thunderbird has 6 interconnect layers,
the AMD Athlon Palomino has 7 interconnect layers,
the AMD Athlon Thoroughbred A has 8 interconnect layers,
and the AMD Athlon Thoroughbred B has 9 interconnect layers.
The Intel Xeon Dunnington has nine copper interconnect layers.
Steps of the BEOL:
- Silicidation of source and drain regions and the polysilicon region.
- Adding a dielectric (first, lower layer is Pre-Metal dielectric, PMD - to isolate metal from silicon and polysilicon), CMPChemical-mechanical planarizationChemical Mechanical Polishing/Planarization is a process of smoothing surfaces with the combination of chemical and mechanical forces. It can be thought of as a hybrid of chemical etching and free abrasive polishing.-Description:...
processing it - Make holes in PMD, make a contacts in them.
- Add metal layer 1
- Add a second dielectric (this time it is Intra-Metal dielectric)
- Make vias through dielectric to connect lower metal with higher metal. Vias filled by Metal CVDChemical vapor depositionChemical vapor deposition is a chemical process used to produce high-purity, high-performance solid materials. The process is often used in the semiconductor industry to produce thin films. In a typical CVD process, the wafer is exposed to one or more volatile precursors, which react and/or...
process.- Repeat steps 4-6 to get all metal layers.
- Add final passivation layer to protect the microchip
Before 1998, practically all chips used aluminum for the metal interconnection layers.
The four metals with the highest electrical conductivity are silver with the highest conductivity, then copper, then gold, then aluminum.
As of 2011, many commercial processes support 2 or 3 metal layers; the most layers supported on a commercial process is 11 layers, and 12 layers are expected to be supported soon.
After BEOL there is a "Backend process" (also called post-fab), which is done not in the cleanroom, often by different company.
It includes wafer test
Wafer testing
Wafer testing is a step performed during semiconductor device fabrication. During this step, performed before a wafer is sent to die preparation, all individual integrated circuits that are present on the wafer are tested for functional defects by applying special test patterns to them. The wafer...
, wafer backgrinding
Wafer backgrinding
Wafer backgrinding is a semiconductor device fabrication step during which wafer thickness is reduced to allow for stacking and high density packaging of integrated circuits ....
, die separation
Die preparation
Die preparation is a step of semiconductor device fabrication during which a wafer is prepared for IC packaging and IC testing. The process of die preparation typically consists of 2 steps: wafer mounting and wafer dicing.-Wafer mounting:...
, die tests, IC packaging
Integrated circuit packaging
Integrated circuit packaging is the final stage of semiconductor device fabrication per se, followed by IC testing.Packaging in ceramic or plastic prevents physical damage and corrosion and supports the electrical contacts required to assemble the integrated circuit into a system.In the integrated...
and final test.
Reading
- Silicon VLSI Technology: Fundamentals, Practice, and Modeling. Prentice Hall 2000, ISBN 0130850373 Chapter 11 "Back End Technology" pages 681-786
- "CMOS: Circuit Design, Layout, and Simulation" Wiley-IEEE, 2010. ISBN 978-0-470-88132-3. http://books.google.com/books?hl=en&lr=&id=N0XgLh2d2pkC pages 177-179 (Chapter 7.2 CMOS Process Integration); pages 199-208 (7.2.2 Backend-of-the-line Integration)