Advanced Microcontroller Bus Architecture
Encyclopedia
The Advanced Microcontroller Bus Architecture (AMBA) is used as the on-chip bus in system-on-a-chip
(SoC) designs. Since its inception, the scope of AMBA has gone far beyond microcontroller devices, and is now widely used on a range of ASIC
and SoC parts including applications processors used in modern portable mobile devices like smartphones.
AMBA was introduced by ARM Ltd in 1996. The first AMBA buses were Advanced System Bus (ASB) and Advanced Peripheral Bus (APB). In its 2nd version, AMBA 2, ARM
added AMBA High-performance Bus (AHB) that is a single clock-edge protocol. In 2003, ARM introduced the 3rd generation, AMBA 3, including AXI to reach even higher performance interconnect and the Advanced Trace Bus (ATB) as part of the CoreSight on-chip debug and trace solution. These protocols are today the de-facto standard for 32-bit embedded processors because they are well documented and can be used without royalties.
The objective of the AMBA specification is to:
The AMBA 4.0 specification defines five buses/interfaces:
The timing aspects and the voltage
levels on the bus are not dictated by the specifications.
In addition to previous release, it has the following features:
A simple transaction on the AHB consists of an address phase and a subsequent data phase (without wait states: only two bus-cycles). Access to the target device is controlled through a MUX
(non-tristate), thereby admitting bus-access to one bus-master at a time.
AHB-Lite is a subset of AHB which is formally defined in the AMBA 3 standard. This subset simplifies the design for a bus with a single master. The ARM AMBA Support FAQ page includes notes on how to integrate a full AHB master into an AHB-lite system and vice versa.
) cores AMBA Products licensable from ARM Limited that implement a digital highway in an SoC for the efficient moving and storing of data using the AMBA protocol specifications. The AMBA family includes AMBA Network Interconnect (NIC-301), SDRAM
and FLASH memory controllers (DMC-34x, SMC-35x), DMA
controllers (DMA-230, DMA-330), level 2 cache controllers (L2C-310), etc.
Some manufacturers utilize AMBA buses for non-ARM designs. As an example Infineon
uses an AMBA bus for the ADM5120 SoC based on the MIPS architecture
.
System-on-a-chip
A system on a chip or system on chip is an integrated circuit that integrates all components of a computer or other electronic system into a single chip. It may contain digital, analog, mixed-signal, and often radio-frequency functions—all on a single chip substrate...
(SoC) designs. Since its inception, the scope of AMBA has gone far beyond microcontroller devices, and is now widely used on a range of ASIC
Application-specific integrated circuit
An application-specific integrated circuit is an integrated circuit customized for a particular use, rather than intended for general-purpose use. For example, a chip designed solely to run a cell phone is an ASIC...
and SoC parts including applications processors used in modern portable mobile devices like smartphones.
AMBA was introduced by ARM Ltd in 1996. The first AMBA buses were Advanced System Bus (ASB) and Advanced Peripheral Bus (APB). In its 2nd version, AMBA 2, ARM
ARM architecture
ARM is a 32-bit reduced instruction set computer instruction set architecture developed by ARM Holdings. It was named the Advanced RISC Machine, and before that, the Acorn RISC Machine. The ARM architecture is the most widely used 32-bit ISA in numbers produced...
added AMBA High-performance Bus (AHB) that is a single clock-edge protocol. In 2003, ARM introduced the 3rd generation, AMBA 3, including AXI to reach even higher performance interconnect and the Advanced Trace Bus (ATB) as part of the CoreSight on-chip debug and trace solution. These protocols are today the de-facto standard for 32-bit embedded processors because they are well documented and can be used without royalties.
Design principles
The important aspect of a SoC is not only which components or blocks it houses, but also how they are interconnected. AMBA is a solution for the blocks to interface with each other.The objective of the AMBA specification is to:
- facilitate right-first-time development of embedded microcontroller products with one or more CPUs, GPUs or signal processors,
- be technology independent, to allow reuse of IP cores, peripheral and system macrocells across diverse IC processes,
- encourage modular system design to improve processor independence, and the development of reusable peripheral and system IP libraries
- minimize silicon infrastructure while supporting high performance and low power on-chip communication.
AMBA protocol specifications
The AMBA specification defines an on-chip communications standard for designing high-performance embedded microcontrollers. It is supported by the ARM Limited corporation with wide cross-industry participation.The AMBA 4.0 specification defines five buses/interfaces:
- Advanced eXtensible Interface (AXI)
- Advanced High-performance Bus (AHB)
- Advanced System Bus (ASB)
- Advanced Peripheral Bus (APB)
- Advanced Trace Bus (ATB).
The timing aspects and the voltage
Voltage
Voltage, otherwise known as electrical potential difference or electric tension is the difference in electric potential between two points — or the difference in electric potential energy per unit charge between two points...
levels on the bus are not dictated by the specifications.
Advanced eXtensible Interface (AXI)
AXI, the third generation of AMBA interface defined in the AMBA 3 specification, is targeted at high performance, high clock frequency system designs and includes features which make it very suitable for high speed sub-micrometer interconnect:- separate address/control and data phases
- support for unaligned data transfers using byte strobes
- burst based transactions with only start address issued
- issuing of multiple outstanding addresses
- easy addition of register stages to provide timing closure.
Advanced High-performance Bus (AHB)
AHB is a bus protocol introduced in Advanced Microcontroller Bus Architecture version 2 published by ARM Ltd company.In addition to previous release, it has the following features:
- single edge clock protocol
- split transactions
- several bus masters
- burst transfers
- pipelined operations
- single-cycle bus master handover
- non-tristate implementation
- large bus-widths (64/128 bit).
A simple transaction on the AHB consists of an address phase and a subsequent data phase (without wait states: only two bus-cycles). Access to the target device is controlled through a MUX
Mux
mux was a windowing system developed by Rob Pike at Bell Labs for the Ninth Edition Research Unix. mux is a predecessor of the Plan 9 windowing systems 8½ and rio, which retain its minimalist user interface.-External links :*...
(non-tristate), thereby admitting bus-access to one bus-master at a time.
AHB-Lite is a subset of AHB which is formally defined in the AMBA 3 standard. This subset simplifies the design for a bus with a single master. The ARM AMBA Support FAQ page includes notes on how to integrate a full AHB master into an AHB-lite system and vice versa.
Advanced Peripheral Bus (APB)
APB is designed for low bandwidth control accesses, for example register interfaces on system peripherals. This bus has an address and data phase similar to AHB, but a much reduced low complexity signal list, for example no bursts.AMBA products
A family of synthesizable intellectual property (IPSemiconductor intellectual property core
In electronic design a semiconductor intellectual property core, IP core, or IP block is a reusable unit of logic, cell, or chip layout design that is the intellectual property of one party. IP cores may be licensed to another party or can be owned and used by a single party alone...
) cores AMBA Products licensable from ARM Limited that implement a digital highway in an SoC for the efficient moving and storing of data using the AMBA protocol specifications. The AMBA family includes AMBA Network Interconnect (NIC-301), SDRAM
SDRAM
Synchronous dynamic random access memory is dynamic random access memory that is synchronized with the system bus. Classic DRAM has an asynchronous interface, which means that it responds as quickly as possible to changes in control inputs...
and FLASH memory controllers (DMC-34x, SMC-35x), DMA
Direct memory access
Direct memory access is a feature of modern computers that allows certain hardware subsystems within the computer to access system memory independently of the central processing unit ....
controllers (DMA-230, DMA-330), level 2 cache controllers (L2C-310), etc.
Some manufacturers utilize AMBA buses for non-ARM designs. As an example Infineon
Infineon Technologies
Infineon Technologies AG is a German semiconductor manufacturer and was founded on April 1, 1999, when the semiconductor operations of the parent company Siemens AG were spun off to form a separate legal entity. , Infineon has 25,149 employees worldwide...
uses an AMBA bus for the ADM5120 SoC based on the MIPS architecture
MIPS architecture
MIPS is a reduced instruction set computer instruction set architecture developed by MIPS Technologies . The early MIPS architectures were 32-bit, and later versions were 64-bit...
.
Competitors
- OpencoresOpenCoresOpenCores is the world's largest open source hardware community developing digital open source hardware through electronic design automation, with a similar ethos to the free software movement. OpenCores hopes to eliminate redundant design work and slash development costs. A number of companies...
Wishbone busWishbone (computer bus)The Wishbone Bus is an open source hardware computer bus intended to let the parts of an integrated circuit communicate with each other. The aim is to allow the connection of differing cores to each other inside of a chip...
- Free and open bus architecture (formerly from Silicore) - IBMIBMInternational Business Machines Corporation or IBM is an American multinational technology and consulting corporation headquartered in Armonk, New York, United States. IBM manufactures and sells computer hardware and software, and it offers infrastructure, hosting and consulting services in areas...
CoreConnectCoreConnectCoreConnect is a microprocessor bus-architecture from IBM for system-on-a-chip designs. Designed to ease the integration and reuse of processor, system, and peripheral cores within standard and custom SoC designs. As a standard SoC design point, it serves as the foundation of IBM or non-IBM devices...
bus technology, used in PowerIBM POWERPOWER is a reduced instruction set computer instruction set architecture developed by IBM. The name is an acronym for Performance Optimization With Enhanced RISC....
systems, but also in many other SoCSystem-on-a-chipA system on a chip or system on chip is an integrated circuit that integrates all components of a computer or other electronic system into a single chip. It may contain digital, analog, mixed-signal, and often radio-frequency functions—all on a single chip substrate...
s like systems with the XilinxXilinxXilinx, Inc. is a supplier of programmable logic devices. It is known for inventing the field programmable gate array and as the first semiconductor company with a fabless manufacturing model....
MicroBlazeMicroBlazeThe MicroBlaze is a soft processor core designed for Xilinx FPGAs from Xilinx. As a soft-core processor, MicroBlaze is implemented entirely in the general-purpose memory and logic fabric of Xilinx FPGAs.-Overview:...
or similar cores - IDTIntegrated Device TechnologyIntegrated Device Technology, Inc. is a publicly traded corporation headquartered in San Jose, California, that designs, manufactures, and markets low-power, high-performance mixed-signal semiconductor solutions for the advanced communications, computing, and consumer industries. The company...
IPBus - AlteraAlteraAltera Corporation is a Silicon Valley manufacturer of PLDs . The company offered its first programmable logic device in 1984. PLDs can be reprogrammed during the design cycle as well as in the field to perform multiple functions, and they support a fairly fast design process...
Avalon - proprietary bus system for Alteras Nios IINios IINios II is a 32-bit embedded-processor architecture designed specifically for the Altera family of FPGAs. Nios II incorporates many enhancements over the original Nios architecture, making it more suitable for a wider range of embedded computing applications, from DSP to system-control.Nios II is...
-SoCSOCSOC or SoC may refer to:Social Networking / Entertainment* Soc.TV, an internet based, social television network* Soldier of ChristBusiness* Sirte Oil Company* South Oil CompanyScience and technology...
s
External links
- AMBA of ARM
- AMBA FAQ - from ARM
- AMBA 2 Specification - from ARM
- AMBA 3 Specification - from ARM
- AHB To Wishbone project page - AHB to Wishbone bridge
- APB eVC (e Verification Component)