Warp (Cypress)
Encyclopedia
Warp is a VHDL low cost development system for CPLD
by Cypress Semiconductor
Corporation. The cost is low (about $99) because of its simple architecture. Warp contains an interactive simulator (Aldec
) and a compiler (Galaxy).
Unlike the IEEE 1164
standard, Warp supports only 6 logic levels: "0", "1", "Z", "L", "H" and "-"; "X" (strong drive logic unknown) and "W" (Weak drive unknown) aren't supported. The arithmetic operators can be supported by system only if the appropriate library is linked.
With Warp a project can be written only with VHDL both with behavioral and structural architecture. Aldec is the simulator that can do pre-synthesis and post-synthesis simulation. Pre-synthesis simulation is useful to verify that VHDL program works as expected and post-synthesis simulation keeps also propagation delay.
At the end of the process ISR, a programming software, generates a "jam" file containing the bit streams needed to programming PLD macrocells.
At the current date (Dec. 2009), Cypress Semiconductor have no longer Warp for sale because license agreement with Alder Simulator expired, however, Cypress still provides technical support for previous customers
CPLD
A complex programmable logic device is a programmable logic device with complexity between that of PALs and FPGAs, and architectural features of both. The building block of a CPLD is the macrocell, which contains logic implementing disjunctive normal form expressions and more specialized logic...
by Cypress Semiconductor
Cypress Semiconductor
Cypress Semiconductor Corporation is a Silicon Valley-based semiconductor design and manufacturing company founded by T. J. Rodgers and others from Advanced Micro Devices. It was formed in 1982 with backing by Sevin Rosen and went public in 1986. The company initially focused on the design and...
Corporation. The cost is low (about $99) because of its simple architecture. Warp contains an interactive simulator (Aldec
Aldec
- Overview :Aldec provides software and hardware used in creation and verification of digital designs targeting FPGA and ASIC technologies. Headquartered in Henderson, Nevada, Aldec also has offices/development centers in Europe, Japan, Israel, India, China, Taiwan, Poland and Ukraine.As a member...
) and a compiler (Galaxy).
Unlike the IEEE 1164
IEEE 1164
The IEEE 1164 standard defines a package design unit that contains declarations that support a uniform representation of a logic value in a VHDL hardware description....
standard, Warp supports only 6 logic levels: "0", "1", "Z", "L", "H" and "-"; "X" (strong drive logic unknown) and "W" (Weak drive unknown) aren't supported. The arithmetic operators can be supported by system only if the appropriate library is linked.
With Warp a project can be written only with VHDL both with behavioral and structural architecture. Aldec is the simulator that can do pre-synthesis and post-synthesis simulation. Pre-synthesis simulation is useful to verify that VHDL program works as expected and post-synthesis simulation keeps also propagation delay.
Projecting steps
- VHDL or Verilog code writing with graphic editor
- Code simulation to verify that program works as expected
- Synthesis after choosing a specific device
- Automatic fitting (mapping logic functions into PLD logic blocks)
- Post synthesis simulation with timing informations
At the end of the process ISR, a programming software, generates a "jam" file containing the bit streams needed to programming PLD macrocells.
At the current date (Dec. 2009), Cypress Semiconductor have no longer Warp for sale because license agreement with Alder Simulator expired, however, Cypress still provides technical support for previous customers