In the semiconductor and electronic design industry, Verilog is a hardware description language used to model electronic systems. Verilog HDL, not to be confused with VHDL , is most commonly used in the design, verification, and implementation of digital logic chips at the register-transfer level...
In electronics, a hardware description language or HDL is any language from a class of computer languages, specification languages, or modeling languages for formal description and design of electronic circuits, and most-commonly, digital logic...
. It includes analog and mixed-signal extensions (AMS) in order to define the behavior of analog and mixed-signal systems. It extends the event-based simulator loops of Verilog/SystemVerilog/VHDL, by a continuous-time simulator, which solves the differential equations in analog-domain. Both domains are coupled: analog events can trigger digital actions and vice versa.
Overview
The Verilog-AMS standard was created with the intent of enabling designers of analog and mixed signal systems and integrated circuits to create and use modules that encapsulate high-level behavioral descriptions as well as structural descriptions of systems and components.
Verilog-AMS is an industry standard modeling language for mixed signal circuits. It provides both continuous-time and event-driven modeling semantics, and so is suitable for analog, digital, and mixed analog/digital circuits. It is particularly well suited for verification of very complex analog, mixed-signal and RF integrated circuits.
In electronics, a hardware description language or HDL is any language from a class of computer languages, specification languages, or modeling languages for formal description and design of electronic circuits, and most-commonly, digital logic...
s (HDLs). As such, they provide sophisticated and powerful language features for definition and synchronization of parallel actions and events. On the other hand, many actions defined in HDL program statements can run in parallel (somewhat similar to threads and tasklets in procedural languages, but much more fine-grained). However, Verilog/AMS can be coupled with procedural languages like the ANSI C language using the Verilog Procedural Interface
Verilog Procedural Interface
The Verilog Procedural Interface , originally known as PLI 2.0, is an interface primarily intended for the C programming language. It allows behavioral Verilog code to invoke C functions, and C functions to invoke standard Verilog system tasks...
of the simulator, which eases testsuite implementation, and allows interaction with legacy code or testbench equipment.
Code example
Verilog/AMS is a superset of the Verilog digital HDL, so all statements in digital domain work as in Verilog
Verilog
In the semiconductor and electronic design industry, Verilog is a hardware description language used to model electronic systems. Verilog HDL, not to be confused with VHDL , is most commonly used in the design, verification, and implementation of digital logic chips at the register-transfer level...
(see there for examples). In analog domain, some new operators are defined, for example the "<+" branch contribution operator. This Verilog-AMS example implements a ideal diode, by defining the current through the branch (a,c) depending on voltage at branch terminals (a), (c), and the ambient temperature of the simulated circuit:
// Ideal Diode
module diode (a, c);
inout a, c;
electrical a, c;
parameter real IS = 1.0e-14; // User-configurable saturation current
real idio;
/**
* Calculate nonlinear current through diode depending on
* - thermal voltage $vt (at ambient temperature of simulated circuit) and
* - voltage between terminals
*/
analog begin
idio = IS * (limexp(V(a,c)/$vt) - 1);
I(a,c) <+ idio;
end
endmodule
For a simple DC voltage source, the branch voltage is set to the constant (DC) value:
// DC Source
module vsrc (p,n);
parameter real dc = 1.0;
inout p;
inout n;
electrical p;
electrical n;
analog begin
// Initial condition to ensure convergence (not required in this particular example, but good coding practice):
@(initial_step)
V(p,n) <+ 0.0 ;
// Assign constant DC voltage at each time step:
V(p,n) <+ dc;
end
endmodule
A sine voltage generator can use the built-in sin function:
// A sinusoidal Source
`include "constants.vams" // for definition of `M_PI = 3.1415....
module vsin (p,n);
parameter real amplitude = 1.0;
parameter real freq = 50.0;
parameter real phase = 0.0;
inout p;
inout n;
electrical p;
electrical n;
analog begin
@(initial_step)
V(p,n) <+ 0.0 ;
V(p,n) <+ amplitude * sin(2.0 * `M_PI * freq * $abstime + phase);
end
endmodule
In the semiconductor and electronic design industry, Verilog is a hardware description language used to model electronic systems. Verilog HDL, not to be confused with VHDL , is most commonly used in the design, verification, and implementation of digital logic chips at the register-transfer level...
Verilog-A is an industry standard modeling language for analog circuits. It is the continuous-time subset of Verilog-AMS.Verilog-A was created out of a need to standardize the Spectre behavioral language in face of competition from VHDL , which was absorbing analog capability from other languages...
VHDL-AMS is a derivative of the hardware description language VHDL . It includes analog and mixed-signal extensions in order to define the behavior of analog and mixed-signal systems ....
I. Miller and T. Cassagnes, "Verilog-AMS Eases Mixed Mode Signal Simulation," Technical Proceedings of the 2000 International Conference on Modeling and Simulation of Microsystems, pp. 305-308, Available: http://www.nsti.org/publ/MSM2000/T31.01.pdf
