Tensilica Instruction Extension refers to the proprietary language that is used to customize the Xtensa processor core architecture.

By using TIE, the user can customize the Xtensa architecture by adding custom instructions and register files, instantiating TIE Ports and Queues for multiprocessor communication, and adding pre-configured extensions (such as Tensilica's DSP). Software applications can greatly benefit from properly targeted user-defined instructions, while TIE ports and TIE queues facilitate multiprocessor communication by addign separate input and output interfaces to the processor core. Using the TIE language and Xtensa Xplorer toolkit, the generation and verification of the instructions used to extend the processor ISA are automated. Such automation helps to reduce the hardware verification time that typically consumes a large percentage of the project duration of a typical hardware developed for the same functionality.

TIE Creation

TIE code can be created in two ways. TIE can be:

1. Manually written and attached to the required processor core.
2. Automatically generated using Xtensa Xpress.

Manual coding is similar to programming using Verilog

Verilog

In the semiconductor and electronic design industry, Verilog is a hardware description language used to model electronic systems. Verilog HDL, not to be confused with VHDL , is most commonly used in the design, verification, and implementation of digital logic chips at the register-transfer level...

, a Hardware description language

Hardware description language

In electronics, a hardware description language or HDL is any language from a class of computer languages, specification languages, or modeling languages for formal description and design of electronic circuits, and most-commonly, digital logic...

. Automatic generation of TIE code is done using Xtensa Xpress tool. This is done by first compiling & executing the code using the Xplorer and Xtensa Xpress tools. Xpress analyses the code that will be executed on the processor and generates additional TIE instructions for the processor core. These additional instructions will be automatically substituted when the C/C++

C++

C++ is a statically typed, free-form, multi-paradigm, compiled, general-purpose programming language. It is regarded as an intermediate-level language, as it comprises a combination of both high-level and low-level language features. It was developed by Bjarne Stroustrup starting in 1979 at Bell...

 compiler generates the assembly code, preventing any manual intervention. This provides a complete user abstraction to the automatic TIE generation process.

Interface to C/C++

TIE extended instructions are called "operations" in TIE language. Since TIE compiler generates compiler intrinsics for each TIE operation, the TIE instructions can be invoked directly using the function call semantics of C language. The C compiler takes care of translating the TIE intrinsics into the appropriate instructions to be executed in the assembly code that is generated.

TIE Compilation

The TIE compiler is used to compile code written in TIE language. TIE compiler automates the generation of the designer defined hardware instructions additions to the processor core.

TIE compilation produces the following outputs:

1. A Modeling Environment that can be simulated using ISS
2. A Compiler Toolchain for the Configured Processor Core that includes the TIE intrinsics to be used
3. Hardware RTL Source Code for TIE and EDA
   EDA
   - Organizations :* Eating Disorders Association, a British medical charity organization, known as beat since February 2007* Economic Development Administration, US agency providing economic grants to communities* Ejército del Aire, Spanish Air Force...
   
    scripts for synthesis and Verification

TIE Testing & Verification

Once the code has been compiled using the TIE compiler, there are minimum two levels of verification & testing required to verify the functionality.

1. Software Testing: Using the intrinsic interfaces of TIE operations from C/C++, the TIEs are first integrated with the C code that tests the required application functionality. After such integration, testing of the software running on the Xtensa core is performed by using the software simulator on PC (The Xtensa simulator on PC is called Instruction Set Simulator - ISS).
2. Hardware Verification: The TIE compiler's output RTL and Netlists are given as input to various simulators like Modelsim. the required functionality of the TIE is verified by hardware simulation. Such verification requires a Hardware/Software co-simulation environment to be prepared, where the required software can be tested for its functionality.

See also

• Xtensa The configurable processor core
• Verilog
  Verilog
  In the semiconductor and electronic design industry, Verilog is a hardware description language used to model electronic systems. Verilog HDL, not to be confused with VHDL , is most commonly used in the design, verification, and implementation of digital logic chips at the register-transfer level...
  
   The hardware description language

External links

• TIE syntax highlight script for Vim editor : http://www.vim.org/scripts/script.php?script_id=1964