TILEPro64
Encyclopedia
TILEPro64 is a multicore processor (Tile processor
) manufactured by Tilera
. It consists of a cache-coherent mesh network of 64 "tiles", where each tile houses a general purpose processor
, cache
, and a non-blocking router, which the tile uses to communicate with the other tiles on the processor.
The short-pipeline, in-order, three-issue cores implement a VLIW
instruction set
. Each core has a register
file and three functional units: two integer arithmetic logic unit
s and a load-store unit. Each of the cores ("tile") has its own L1 and L2 caches plus an overall virtual L3 cache which is an aggregate of all the L2 caches. A core is able to run a full operating system on its own or multiple cores can be used to run a symmetrical multi-processing operating system.
TILEPro64 has four DDR2
controllers at up to 800MT/s, two 10-gigabit Ethernet
XAUI interfaces, two four-lane PCIe interfaces, and a "flexible" input/output interface, which can be software-configured to handle a number of protocols. The processor is fabricated using a 90 nm process and runs at speeds of 600 to 866 MHz.
According to the company, Tilera targets the chip at networking equipment, digital video, and wireless infrastructure markets where the demands for computing processing are high. More recently, Tilera has positioned this processor in the cloud computing space with an 8-processor (512-core) 2U server built by Quanta Computer.
TILEPro is supported by the Linux kernel
since version 2.6.36.
The TILEPro family incorporates a number of enhancements over Tilera's first generation TILE64
family:
The networking software company 6WIND
provides high-performance packet processing software for the TILEPro64 platform.
Tile processor
Tile processors are multicore or manycore chips that contain one-dimensional, or more commonly, two-dimensional arrays of identical tiles. Each tile comprises a compute unit , caches and a switch...
) manufactured by Tilera
Tilera
Tilera Corporation is a fabless semiconductor company focusing on scalable multicore embedded processor design. The company is currently shipping multiple processors, including the TILE64, TILEPro64, and the TILEPro36, TILE-Gx36, TILE-Gx16 and TILE-Gx9...
. It consists of a cache-coherent mesh network of 64 "tiles", where each tile houses a general purpose processor
Microprocessor
A microprocessor incorporates the functions of a computer's central processing unit on a single integrated circuit, or at most a few integrated circuits. It is a multipurpose, programmable device that accepts digital data as input, processes it according to instructions stored in its memory, and...
, cache
CPU cache
A CPU cache is a cache used by the central processing unit of a computer to reduce the average time to access memory. The cache is a smaller, faster memory which stores copies of the data from the most frequently used main memory locations...
, and a non-blocking router, which the tile uses to communicate with the other tiles on the processor.
The short-pipeline, in-order, three-issue cores implement a VLIW
Very long instruction word
Very long instruction word or VLIW refers to a CPU architecture designed to take advantage of instruction level parallelism . A processor that executes every instruction one after the other may use processor resources inefficiently, potentially leading to poor performance...
instruction set
Instruction set
An instruction set, or instruction set architecture , is the part of the computer architecture related to programming, including the native data types, instructions, registers, addressing modes, memory architecture, interrupt and exception handling, and external I/O...
. Each core has a register
Processor register
In computer architecture, a processor register is a small amount of storage available as part of a CPU or other digital processor. Such registers are addressed by mechanisms other than main memory and can be accessed more quickly...
file and three functional units: two integer arithmetic logic unit
Arithmetic logic unit
In computing, an arithmetic logic unit is a digital circuit that performs arithmetic and logical operations.The ALU is a fundamental building block of the central processing unit of a computer, and even the simplest microprocessors contain one for purposes such as maintaining timers...
s and a load-store unit. Each of the cores ("tile") has its own L1 and L2 caches plus an overall virtual L3 cache which is an aggregate of all the L2 caches. A core is able to run a full operating system on its own or multiple cores can be used to run a symmetrical multi-processing operating system.
TILEPro64 has four DDR2
DDR2
DDR2 may refer to:* DDR2 SDRAM, the computer memory technology* Dance Dance Revolution 2ndMix, the video game* DDR2 , a human gene...
controllers at up to 800MT/s, two 10-gigabit Ethernet
Ethernet
Ethernet is a family of computer networking technologies for local area networks commercially introduced in 1980. Standardized in IEEE 802.3, Ethernet has largely replaced competing wired LAN technologies....
XAUI interfaces, two four-lane PCIe interfaces, and a "flexible" input/output interface, which can be software-configured to handle a number of protocols. The processor is fabricated using a 90 nm process and runs at speeds of 600 to 866 MHz.
According to the company, Tilera targets the chip at networking equipment, digital video, and wireless infrastructure markets where the demands for computing processing are high. More recently, Tilera has positioned this processor in the cloud computing space with an 8-processor (512-core) 2U server built by Quanta Computer.
TILEPro is supported by the Linux kernel
Linux kernel
The Linux kernel is an operating system kernel used by the Linux family of Unix-like operating systems. It is one of the most prominent examples of free and open source software....
since version 2.6.36.
Technology
Various sources have stated the specifications of processors in the TILEPro family:- 64 RISC processor cores
- 16 KBKilobyteThe kilobyte is a multiple of the unit byte for digital information. Although the prefix kilo- means 1000, the term kilobyte and symbol KB have historically been used to refer to either 1024 bytes or 1000 bytes, dependent upon context, in the fields of computer science and information...
L1 instruction and 8 KB L1 data cache per core - 64 KB L2 cache per core
- 16 KB
- 4MB L3 cache is achieved through the sharing of other tiles L2 caches with hardwared-managed coherencyCache coherenceIn computing, cache coherence refers to the consistency of data stored in local caches of a shared resource.When clients in a system maintain caches of a common memory resource, problems may arise with inconsistent data. This is particularly true of CPUs in a multiprocessing system...
- 90 nm90 nanometerThe 90 nm process refers to the level of CMOS process technology that was reached in the 2002–2003 timeframe, by most leading semiconductor companies, like Intel, AMD, Infineon, Texas Instruments, IBM, and TSMC....
manufacturing process at TSMC - 4 integrated memory controllerMemory controllerThe memory controller is a digital circuit which manages the flow of data going to and from the main memory. It can be a separate chip or integrated into another chip, such as on the die of a microprocessor...
s supporting DDR2 SDRAMDDR2 SDRAMDDR2 SDRAM is a double data rate synchronous dynamic random-access memory interface. It supersedes the original DDR SDRAM specification and has itself been superseded by DDR3 SDRAM...
at up to 800MT/s- supports up to 64GB of attached DDR2 memory
- Integrated high-speed I/O
- Two 4-lane PCI ExpressPCI ExpressPCI Express , officially abbreviated as PCIe, is a computer expansion card standard designed to replace the older PCI, PCI-X, and AGP bus standards...
Gen1 interfaces, with root or endpoint capability - Two 10Gbps Ethernet XAUIXAUIXAUI is a standard for extending the XGMII between the MAC and PHY layer of 10 Gigabit Ethernet . XAUI is pronounced "zowie", a concatenation of the Roman numeral X, meaning ten, and the initials of "Attachment Unit Interface"...
interfaces - Two 10/100/1000 Mbps Ethernet RGMII interfaces
- Two 4-lane PCI Express
- Power consumption in the range of 19 - 23 Watts
The TILEPro family incorporates a number of enhancements over Tilera's first generation TILE64
TILE64
TILE64 is a multicore processor manufactured by Tilera. It consists of a mesh network of 64 "tiles", where each tile houses a general purpose processor, cache, and a non-blocking router, which the tile uses to communicate with the other tiles on the processor....
family:
- "Distributed Dynamic Cache" (DDC) system that uses a separate mesh network to manage cache-coherency
- "TileDirect" I/O enables direct transfer of network data coherently into the processor caches
- Double the L1 i-cache (from 8KB to 16KB), double the L2 associativity
- Memory "striping" on the DDR2 interfaces to balance the loading
- Instruction set enhancements for multimedia, unaligned data access, offset ld/st instructions and memory access hints
The networking software company 6WIND
6WIND
6WIND S.A. is a privately held company that provides packet processing software used by OEM companies to meet both the wire-speed performance and time-to-market requirements of mobile infrastructure, network security, high-frequency trading and deep packet inspection applications...
provides high-performance packet processing software for the TILEPro64 platform.
External links
- Tilera Website
- http://www.theregister.co.uk/2008/09/23/tilera_cpu_upgrade/
- http://www.linleygroup.com/npu/Newsletter/wire080924.html#2