Socket G3 Memory Extender
Encyclopedia
The Socket G3 Memory Extender or in short G3MX is Advanced Micro Devices
' solution to the problem of connecting large amounts of memory to a single microprocessor. The G3MX was expected to be available on future AMD 800S series chipset
for server market starting from 2009, but was officially cancelled together with the cancellation of Socket G3
in early 2008.
Electrical limitations preclude connecting more than 2 unbuffered DDR SDRAM
DIMM
s or 4 buffered DIMMs to a single shared bus. It is also impractical to manufacture a single chip with more than two DDR memory buses (channels). Thus, it is impossible to connect more than 8 DIMMs to a single chip. This is typically the per-processor limitation as well.
The obvious solution is to use a narrower, higher-speed bus to interface to memory, and to implement it as a point-to-point link, daisy-chaining
additional modules. However, Intel have made two attempts at this, neither hugely successful:
AMD's answer to this is the G3MX chip. This is very similar to the AMB, but is intended to be placed on the motherboard
, not on the DIMM. It can connect to multiple DIMMs but, to minimize latency, is not designed to be daisy-chained.
The G3MX has an asymmetrical link to the processor, to match typical memory usage patterns. 20 differential signals supply read data to the processor, and 13 differential signals receive commands and write data. This totals 66 pins, less than half of what is required for a DDR2 or DDR3 interface. Thus, a processor can easily have 4 G3MX memory interfaces, each with 4 buffered DIMMs attached, allowing up to 16 DIMMs to feed one processor.
Advanced Micro Devices
Advanced Micro Devices, Inc. or AMD is an American multinational semiconductor company based in Sunnyvale, California, that develops computer processors and related technologies for commercial and consumer markets...
' solution to the problem of connecting large amounts of memory to a single microprocessor. The G3MX was expected to be available on future AMD 800S series chipset
AMD 800 chipset series
The AMD 800 chipset series is a set of chipsets developed by AMD, released in 2009. The chipset series was revealed in its presentation slides during the AMD Financial Analyst Day 2007 held on December 13, 2007...
for server market starting from 2009, but was officially cancelled together with the cancellation of Socket G3
Socket G3
The Socket G3, originally as part of the codenamed Piranha server platform, was supposed to be the intermediate successor to Socket F and Socket F+ to be used in AMD Opteron processor for dual-processor and above server platforms scheduled to be launched 2009...
in early 2008.
Electrical limitations preclude connecting more than 2 unbuffered DDR SDRAM
DDR SDRAM
Double data rate synchronous dynamic random access memory is a class of memory integrated circuits used in computers. DDR SDRAM has been superseded by DDR2 SDRAM and DDR3 SDRAM, neither of which are either forward or backward compatible with DDR SDRAM, meaning that DDR2 or DDR3 memory modules...
DIMM
DIMM
A DIMM or dual in-line memory module, comprises a series of dynamic random-access memory integrated circuits. These modules are mounted on a printed circuit board and designed for use in personal computers, workstations and servers...
s or 4 buffered DIMMs to a single shared bus. It is also impractical to manufacture a single chip with more than two DDR memory buses (channels). Thus, it is impossible to connect more than 8 DIMMs to a single chip. This is typically the per-processor limitation as well.
The obvious solution is to use a narrower, higher-speed bus to interface to memory, and to implement it as a point-to-point link, daisy-chaining
Daisy chain
Daisy chain may refer to a daisy garland created from daisy flowers, the original meaning and the one from which the following derive by analogy:*Daisy chain *Daisy chain *Daisy chain...
additional modules. However, Intel have made two attempts at this, neither hugely successful:
- RDRAMRDRAMDirect Rambus DRAM or DRDRAM is a type of synchronous dynamic RAM. RDRAM was developed by Rambus inc., in the mid-1990s as a replacement for then-prevalent DIMM SDRAM memory architecture....
implements the bus on a DRAM chip. However, the high-speed circuitry increased power consumption, and the daisy-chaining caused significantly higher memory latency. Because it is difficult to implement high-speed circuitry on the same semiconductor process, costs were high. - FB-DIMMs add a separate memory controller chip to each memory DIMM. This "advanced memory buffer" (also known by the abbreviation AMB) provides the necessary high-speed circuitry. However, the same power and heat problems have arisen.
AMD's answer to this is the G3MX chip. This is very similar to the AMB, but is intended to be placed on the motherboard
Motherboard
In personal computers, a motherboard is the central printed circuit board in many modern computers and holds many of the crucial components of the system, providing connectors for other peripherals. The motherboard is sometimes alternatively known as the mainboard, system board, or, on Apple...
, not on the DIMM. It can connect to multiple DIMMs but, to minimize latency, is not designed to be daisy-chained.
The G3MX has an asymmetrical link to the processor, to match typical memory usage patterns. 20 differential signals supply read data to the processor, and 13 differential signals receive commands and write data. This totals 66 pins, less than half of what is required for a DDR2 or DDR3 interface. Thus, a processor can easily have 4 G3MX memory interfaces, each with 4 buffered DIMMs attached, allowing up to 16 DIMMs to feed one processor.