Program status word
Encyclopedia
The Program status word (PSW) is an IBM System/360 architecture
and successors control register which performs the function of a Status register
in other architectures, and more.
Although certain fields within the PSW may be tested or set by using non-privileged instructions, testing or setting the remaining fields may only be accomplished by using privileged instructions.
Contained within the PSW are certainly the zero (non-zero) and carry (borrow) flags and similar flags of other architectures' status registers, in this case encoded as a condition code with values from 0 to 15, representing the arithmetic sum of the four condition code bit values, 23 + 22 + 21 + 20.
The 64-bit PSW describes (among other things)
In the early instances of the architecture (System/360 and early System/370), the instruction address was 24 bits; in later instances (late System/370), the instruction address was 31 bits plus a mode bit (24 bit addressing mode if zero; 31 bit addressing mode if one) for a total of 32 bits.
In the present instances of the architecture (z/System), the instruction address is 64 bits and the PSW itself is 128 bits.
Other than the general purpose and floating point registers, which are loaded by non-privileged instructions, the entire context of a program may be loaded by the privileged Load program status word instruction (LPSW).
There is no corresponding Store program status word instruction. Storing a PSW is only accomplished through one of the several defined system interruptions (the associated "old PSW") and which also causes another PSW to be loaded (the associated "new PSW"). Once the interruption has been serviced, the associated "old PSW" is loaded and the interrupted program resumes.
IBM System/360 architecture
The IBM System/360 architecture is the model independent architecture for the entire S/360 line of computers. The elements of the architecture are documented in the IBM System/360 Principles of Operation and the IBM System/360 I/O Interface Channel to Control Unit Original Equipment Manufacturers'...
and successors control register which performs the function of a Status register
Status register
A status register or flag register is a collection of flag bits for a processor. An example is the FLAGS register of the x86 architecture....
in other architectures, and more.
Although certain fields within the PSW may be tested or set by using non-privileged instructions, testing or setting the remaining fields may only be accomplished by using privileged instructions.
Contained within the PSW are certainly the zero (non-zero) and carry (borrow) flags and similar flags of other architectures' status registers, in this case encoded as a condition code with values from 0 to 15, representing the arithmetic sum of the four condition code bit values, 23 + 22 + 21 + 20.
The 64-bit PSW describes (among other things)
- Interrupt masks
- Privilege states
- Condition code
- Instruction address
In the early instances of the architecture (System/360 and early System/370), the instruction address was 24 bits; in later instances (late System/370), the instruction address was 31 bits plus a mode bit (24 bit addressing mode if zero; 31 bit addressing mode if one) for a total of 32 bits.
In the present instances of the architecture (z/System), the instruction address is 64 bits and the PSW itself is 128 bits.
Other than the general purpose and floating point registers, which are loaded by non-privileged instructions, the entire context of a program may be loaded by the privileged Load program status word instruction (LPSW).
There is no corresponding Store program status word instruction. Storing a PSW is only accomplished through one of the several defined system interruptions (the associated "old PSW") and which also causes another PSW to be loaded (the associated "new PSW"). Once the interruption has been serviced, the associated "old PSW" is loaded and the interrupted program resumes.