Processor supplementary capability
Encyclopedia
A processor supplementary capability is a feature that has been added to an existing central processing unit design after the initial introduction of that design to the marketplace.
A supplementary capability increases the usefulness of the processor design, allowing it to compete more favorably with competitors and giving consumers a reason to upgrade, while retaining backwards compatibility with the original design.
The CPU supplementary instruction capability does not as a rule apply to 8 or 16 bit CPUs, as many of these CPUs are used mostly as microcontrollers. On modern 32 and 64 bit CPUs the processor supplementary capability does not extend to Floating Point Units (FPUs) or Memory Management Units (MMUs) as these are considered to be fundamental core functionalities. Extensions to the core functionalities of the MMU and FPU may be considered CPU extensions however.
Supplemental instruction programming options
Should the needed instructions not be there a fall back to a (presumably slower or otherwise less desirable) alternative technique can be initiated or else the program may be set to run with reduced functionality.
By using a lowest common denominator strategy (avoiding use of processor supplementary capabilities), programs can be kept portable across all machines of the same architecture.
have seen many new capabilities introduced over several generations of design.
Some of these capabilities have then seen widespread adoption by programmers, spurring consumer upgrades and making the previous generations of processors obsolete.
DE Debugging Extensions
PSE Page Size Extensions
TSC Time Stamp Counter
MSR RDMSR and WRMSR Support
PAE Physical Address Extensions
MCE Machine Check Exception
CXS CMPXCHG8B Instruction
APIC APIC on Chip
MTRR Memory Type Range Register
PGE PTE Global Bit
MCA Machine Check Architecture
CMOV Conditional Move and Compare Instructions
architecture. These instructions were added to later production processors, and are not part of the original IA-32 instruction set. Programs containing these instructions may not operate correctly on all machines in the IA-32 family:
A supplementary capability increases the usefulness of the processor design, allowing it to compete more favorably with competitors and giving consumers a reason to upgrade, while retaining backwards compatibility with the original design.
The CPU supplementary instruction capability does not as a rule apply to 8 or 16 bit CPUs, as many of these CPUs are used mostly as microcontrollers. On modern 32 and 64 bit CPUs the processor supplementary capability does not extend to Floating Point Units (FPUs) or Memory Management Units (MMUs) as these are considered to be fundamental core functionalities. Extensions to the core functionalities of the MMU and FPU may be considered CPU extensions however.
Historical reasoning
The supplementary instructions feature has always been assumed to mean fixed sets of instructions that are not obligatory across all CPUs in a CPU family. Supplementary instructions will simply not be found on all processors within that family. A programmer who wishes to use a supplementary feature of a CPU is faced with a couple of choices.Supplemental instruction programming options
- The operating system (kernel) and systems programmer (programs) may choose to design the systems software so that it mandatorily uses that feature and therefore can only be run on the more recent processors that have that feature.
- On the other hand the system programmer may write or use existing software libraries to determine whether the processor it is running on has a particular feature (or set of instructions).
Should the needed instructions not be there a fall back to a (presumably slower or otherwise less desirable) alternative technique can be initiated or else the program may be set to run with reduced functionality.
- In other cases, an operating systemOperating systemAn operating system is a set of programs that manage computer hardware resources and provide common services for application software. The operating system is the most important type of system software in a computer system...
may mimic the new features for older processors, though often with reduced performance.
By using a lowest common denominator strategy (avoiding use of processor supplementary capabilities), programs can be kept portable across all machines of the same architecture.
CPU families affected
Some popular processor architectures such as x86, 68000, and MIPSMIPS architecture
MIPS is a reduced instruction set computer instruction set architecture developed by MIPS Technologies . The early MIPS architectures were 32-bit, and later versions were 64-bit...
have seen many new capabilities introduced over several generations of design.
Some of these capabilities have then seen widespread adoption by programmers, spurring consumer upgrades and making the previous generations of processors obsolete.
x86 capability flags
VME Virtual 8086 Mode EnhancementDE Debugging Extensions
PSE Page Size Extensions
TSC Time Stamp Counter
Time Stamp Counter
The Time Stamp Counter is a 64-bit register present on all x86 processors since the Pentium. It counts the number of ticks since reset. The instruction "RDTSC" returns the TSC in EDX:EAX. In x86_64 mode, RDTSC also clears the higher 32 bits of RAX. Its opcode is 0F 31. Pentium competitors such as...
MSR RDMSR and WRMSR Support
PAE Physical Address Extensions
MCE Machine Check Exception
Machine Check Exception
A Machine Check Exception is a type of computer hardware error that occurs when a computer's central processing unit detects a hardware problem....
CXS CMPXCHG8B Instruction
APIC APIC on Chip
MTRR Memory Type Range Register
PGE PTE Global Bit
MCA Machine Check Architecture
Machine check architecture
In computing, Machine Check Architecture refers to a mechanism in which the CPU reports hardware errors to the operating system.Intel's Pentium 4, Intel Xeon, P6 family processors as well as the Itanium architecture implement a machine check architecture that provides a mechanism for detecting and...
CMOV Conditional Move and Compare Instructions
Supplementary Capabilities Not Represented By Flags
- 3DNow!3DNow!3DNow! is an extension to the x86 instruction set developed by Advanced Micro Devices . It adds single instruction multiple data instructions to the base x86 instruction set, enabling it to perform simple vector processing, which improves the performance of many graphic-intensive applications...
- Page Attribute TablePage Attribute TableThe page attribute table is a processor supplementary capability extension to the page table format of certain x86 and x86-64 microprocessors...
(PAT) - MMX
- SSEStreaming SIMD ExtensionsIn computing, Streaming SIMD Extensions is a SIMD instruction set extension to the x86 architecture, designed by Intel and introduced in 1999 in their Pentium III series processors as a reply to AMD's 3DNow! . SSE contains 70 new instructions, most of which work on single precision floating point...
Processor Supplementary Instructions
Processor Supplementary Instructions are instructions that have been implemented on certain processors within a family, but are not present on all processors within a particular family.IA-32
The following instructions are considered to be processor supplementary instructions on IA-32IA-32
IA-32 , also known as x86-32, i386 or x86, is the CISC instruction-set architecture of Intel's most commercially successful microprocessors, and was first implemented in the Intel 80386 as a 32-bit extension of x86 architecture...
architecture. These instructions were added to later production processors, and are not part of the original IA-32 instruction set. Programs containing these instructions may not operate correctly on all machines in the IA-32 family:
- bswap
- cmov
- cmova
- cmovae
- cmovb
- cmovbe
- cmovc
- cmove
- cmovg
- cmovge
- cmovl
- cmovle
- cmovna
- cmovnae
- cmovnb
- cmovnbe
- cmovnc
- cmovng
- cmovnge
- cmovnl
- cmovnle
- cmovno
- cmovnp
- cmovns
- cmovnz
- cmovo
- cmovp
- cmovpe
- cmovpo
- cmovs
- cmovz
- cpuidCPUIDThe CPUID opcode is a processor supplementary instruction for the x86 architecture. It was introduced by Intel in 1993 when it introduced the Pentium and SL-Enhanced 486 processors....
- fcmovFCMOVFCMOV is a floating point conditional move opcode of the Intel x86 architecture, first introduced in Pentium Pro processors. It copies the contents of one of the floating point stack register, depending on the contents of EFLAGS integer flag register, to the ST register...
- fcomi
- nopl
- rdpmc
- rdtsc
- syscall
- sysenter
- sysexit
- sysret
- ud2
- xsave
- xrstor
FPU and MMU Capability
The FPU (Floating Point Unit) maths co-processing capability is available on all x86 processors since the 80486DX series. The FPU and MMU instruction sets (for the X86 family) have not been considered supplementary instructions since their introduction due to their importance to core CPU functionality.See also
- x86 instruction listingsX86 instruction listingsThe x86 instruction set has been extended several times, introducing wider registers and datatypes and/or new functionality.-x86 integer instructions:...
- Processor Supplementary Instructions For The i686