PIC microcontroller
Encyclopedia
Harvard architecture
The Harvard architecture is a computer architecture with physically separate storage and signal pathways for instructions and data. The term originated from the Harvard Mark I relay-based computer, which stored instructions on punched tape and data in electro-mechanical counters...
microcontroller
Microcontroller
A microcontroller is a small computer on a single integrated circuit containing a processor core, memory, and programmable input/output peripherals. Program memory in the form of NOR flash or OTP ROM is also often included on chip, as well as a typically small amount of RAM...
s made by Microchip Technology
Microchip Technology
Microchip Technology is an American manufacturer of microcontroller, memory and analog semiconductors. Its products include microcontrollers , Serial EEPROM devices, Serial SRAM devices, KEELOQ devices, radio frequency devices, thermal, power and battery management analog devices, as well as...
, derived from the PIC1650 originally developed by General Instrument
General Instrument
General Instrument was an electronics manufacturer based in Horsham, PA specializing in semiconductors and cable television equipment. The company was active until 1997, when it split into which was later acquired by Vishay Intertechnology in 2001, CommScope and NextLevel Systems General...
's Microelectronics Division. The name PIC initially referred to "Peripheral Interface Controller".
PICs are popular with both industrial developers and hobbyists alike due to their low cost, wide availability, large user base, extensive collection of application notes, availability of low cost or free development tools, and serial programming (and re-programming with flash memory) capability.
Microchip announced on February 2008 the shipment of its six billionth PIC processor.
Core architecture
The PIC architecture is characterized by its multiple attributes:- Separate code and data spaces (Harvard architectureHarvard architectureThe Harvard architecture is a computer architecture with physically separate storage and signal pathways for instructions and data. The term originated from the Harvard Mark I relay-based computer, which stored instructions on punched tape and data in electro-mechanical counters...
) for devices other than PIC32, which has a Von Neumann architectureVon Neumann architectureThe term Von Neumann architecture, aka the Von Neumann model, derives from a computer architecture proposal by the mathematician and early computer scientist John von Neumann and others, dated June 30, 1945, entitled First Draft of a Report on the EDVAC...
. - A small number of fixed length instructions
- Most instructions are single cycle execution (2 clock cycles, or 4 clock cycles in 8-bit models), with one delay cycle on branches and skips
- One accumulatorAccumulator (computing)In a computer's central processing unit , an accumulator is a register in which intermediate arithmetic and logic results are stored. Without a register like an accumulator, it would be necessary to write the result of each calculation to main memory, perhaps only to be read right back again for...
(W0), the use of which (as source operand) is implied (i.e. is not encoded in the opcode) - All RAM locations function as registers as both source and/or destination of math and other functions.http://ww1.microchip.com/downloads/en/DeviceDoc/35007b.pdf
- A hardware stack for storing return addresses
- A fairly small amount of addressable data space (typically 256 bytes), extended through banking
- Data space mapped CPU, port, and peripheral registers
- The program counter is also mapped into the data space and writable (this is used to implement indirect jumps).
There is no distinction between memory space and register space because the RAM serves the job of both memory and registers, and the RAM is usually just referred to as the register file or simply as the registers.
Data space (RAM)
PICs have a set of registers that function as general purpose RAM. Special purpose control registers for on-chip hardware resources are also mapped into the data space. The addressability of memory varies depending on device series, and all PIC devices have some banking mechanismBank switching
Bank switching is a technique to increase the amount of usable memory beyond the amount directly addressable by the processor. It can be used to configure a system differently at different times; for example, a ROM required to start a system from diskette could be switched out when no longer...
to extend addressing to additional memory. Later series of devices feature move instructions which can cover the whole addressable space, independent of the selected bank. In earlier devices, any register move had to be achieved via the accumulator.
To implement indirect addressing, a "file select register" (FSR) and "indirect register" (INDF) are used. A register number is written to the FSR, after which reads from or writes to INDF will actually be to or from the register pointed to by FSR. Later devices extended this concept with post- and pre- increment/decrement for greater efficiency in accessing sequentially stored data. This also allows FSR to be treated almost like a stack pointer (SP).
External data memory is not directly addressable except in some high pin count PIC18 devices.
Code space
The code space is generally implemented as ROMRead-only memory
Read-only memory is a class of storage medium used in computers and other electronic devices. Data stored in ROM cannot be modified, or can be modified only slowly or with difficulty, so it is mainly used to distribute firmware .In its strictest sense, ROM refers only...
, EPROM
EPROM
An EPROM , or erasable programmable read only memory, is a type of memory chip that retains its data when its power supply is switched off. In other words, it is non-volatile. It is an array of floating-gate transistors individually programmed by an electronic device that supplies higher voltages...
or flash ROM
Flash memory
Flash memory is a non-volatile computer storage chip that can be electrically erased and reprogrammed. It was developed from EEPROM and must be erased in fairly large blocks before these can be rewritten with new data...
. In general, external code memory is not directly addressable due to the lack of an external memory interface. The exceptions are PIC17 and select high pin count PIC18 devices.
Word size
All PICs handle (and address) data in 8-bit chunks. However, the unit of addressability of the code space is not generally the same as the data space. For example, PICs in the baseline and mid-range families have program memory addressable in the same wordsize as the instruction width, i.e. 12 or 14 bits respectively. In contrast, in the PIC18 series, the program memory is addressed in 8-bit increments (bytes), which differs from the instruction width of 16 bits.In order to be clear, the program memory capacity is usually stated in number of (single word) instructions, rather than in bytes.
Stacks
PICs have a hardware call stackCall stack
In computer science, a call stack is a stack data structure that stores information about the active subroutines of a computer program. This kind of stack is also known as an execution stack, control stack, run-time stack, or machine stack, and is often shortened to just "the stack"...
, which is used to save return addresses. The hardware stack is not software accessible on earlier devices, but this changed with the 18 series devices.
Hardware support for a general purpose parameter stack was lacking in early series, but this greatly improved in the 18 series, making the 18 series architecture more friendly to high level language compilers.
Instruction set
A PIC's instructions vary from about 35 instructions for the low-end PICs to over 80 instructions for the high-end PICs. The instruction set includes instructions to perform a variety of operations on registers directly, the accumulatorAccumulator (computing)
In a computer's central processing unit , an accumulator is a register in which intermediate arithmetic and logic results are stored. Without a register like an accumulator, it would be necessary to write the result of each calculation to main memory, perhaps only to be read right back again for...
and a literal constant or the accumulator and a register, as well as for conditional execution, and program branching.
Some operations, such as bit setting and testing, can be performed on any numbered register, but bi-operand arithmetic operations always involve W (the accumulator), writing the result back to either W or the other operand register. To load a constant, it is necessary to load it into W before it can be moved into another register. On the older cores, all register moves needed to pass through W, but this changed on the "high end" cores.
PIC cores have skip instructions which are used for conditional execution and branching. The skip instructions are 'skip if bit set' and 'skip if bit not set'. Because cores before PIC18 had only unconditional branch instructions, conditional jumps are implemented by a conditional skip (with the opposite condition) followed by an unconditional branch. Skips are also of utility for conditional execution of any immediate single following instruction.
The 18 series implemented shadow registers which save several important registers during an interrupt, providing hardware support for automatically saving processor state when servicing interrupts.
In general, PIC instructions fall into 5 classes:
- Operation on working register (WREG) with 8-bit immediate ("literal") operand. E.g.
movlw(move literal to WREG),andlw(AND literal with WREG). One instruction peculiar to the PIC isretlw, load immediate into WREG and return, which is used with computed branchBranch (computer science)A branch is sequence of code in a computer program which is conditionally executed depending on whether the flow of control is altered or not . The term can be used when referring to programs in high level languages as well as program written in machine code or assembly language...
es to produce lookup tableLookup tableIn computer science, a lookup table is a data structure, usually an array or associative array, often used to replace a runtime computation with a simpler array indexing operation. The savings in terms of processing time can be significant, since retrieving a value from memory is often faster than...
s. - Operation with WREG and indexed register. The result can be written to either the Working register (e.g.
addwf reg,w). or the selected register (e.g.addwf reg,f). - Bit operations. These take a register number and a bit number, and perform one of 4 actions: set or clear a bit, and test and skip on set/clear. The latter are used to perform conditional branches. The usual ALU status flags are available in a numbered register so operations such as "branch on carry clear" are possible.
- Control transfers. Other than the skip instructions previously mentioned, there are only two:
gotoandcall. - A few miscellaneous zero-operand instructions, such as return from subroutine, and
sleepto enter low-power mode.
Performance
The architectural decisions are directed at the maximization of speed-to-cost ratio. The PIC architecture was among the first scalar CPU designs, and is still among the simplest and cheapest. The Harvard architecture—in which instructions and data come from separate sources—simplifies timing and microcircuit design greatly, and this benefits clock speed, price, and power consumption.The PIC instruction set is suited to implementation of fast lookup tables in the program space. Such lookups take one instruction and two instruction cycles. Many functions can be modeled in this way. Optimization is facilitated by the relatively large program space of the PIC (e.g. 4096 x 14-bit words on the 16F690) and by the design of the instruction set, which allows for embedded constants. For example, a branch instruction's target may be indexed by W, and execute a "RETLW" which does as it is named - return with literal in W.
Interrupt latency is constant at three instruction cycles. External interrupts have to be synchronized with the four clock instruction cycle, otherwise there can be a one instruction cycle jitter. Internal interrupts are already synchronized. The constant interrupt latency allows PICs to achieve interrupt driven low jitter timing sequences. An example of this is a video sync pulse generator. This is no longer true in the newest PIC models, because they have a synchronous interrupt latency of three or four cycles.
Advantages
The PIC architectures have these advantages:- Small instruction set to learn
- RISCReduced instruction set computerReduced instruction set computing, or RISC , is a CPU design strategy based on the insight that simplified instructions can provide higher performance if this simplicity enables much faster execution of each instruction. A computer based on this strategy is a reduced instruction set computer...
architecture - Built in oscillator with selectable speeds
- Easy entry level, in circuit programming plus in circuit debugging PICKitPICKitPICkit is a family of programmers for PIC microcontrollers made by Microchip Technology. They are used to program and debug microcontrollers, as well as program EEPROM...
units available from Microchip.com for less than $50 - Inexpensive microcontrollers
- Wide range of interfaces including I²CI²CI²C is a multi-master serial single-ended computer bus invented by Philips that is used to attach low-speed peripherals to a motherboard, embedded system, cellphone, or other electronic device. Since the mid 1990s, several competitors I²C ("i-squared cee" or "i-two cee"; Inter-Integrated Circuit;...
, SPISerial Peripheral Interface BusThe Serial Peripheral Interface Bus or SPI bus is a synchronous serial data link standard named by Motorola that operates in full duplex mode. Devices communicate in master/slave mode where the master device initiates the data frame. Multiple slave devices are allowed with individual slave select ...
, USB, USARTUniversal asynchronous receiver/transmitterA universal asynchronous receiver/transmitter, abbreviated UART , is a type of "asynchronous receiver/transmitter", a piece of computer hardware that translates data between parallel and serial forms. UARTs are commonly used in conjunction with communication standards such as EIA RS-232, RS-422 or...
, A/DAnalog-to-digital converterAn analog-to-digital converter is a device that converts a continuous quantity to a discrete time digital representation. An ADC may also provide an isolated measurement...
, programmable comparators, PWMPulse-width modulationPulse-width modulation , or pulse-duration modulation , is a commonly used technique for controlling power to inertial electrical devices, made practical by modern electronic power switches....
, LINLocal Interconnect NetworkThe LIN-Bus is a vehicle bus standard or computer networking bus-system used within current automotive network architectures....
, CANController Area NetworkController–area network is a vehicle bus standard designed to allow microcontrollers and devices to communicate with each other within a vehicle without a host computer....
, PSPParallel slave portA parallel slave port is an interface found on some PIC microcontrollers. It allows 8-bit asynchronous bidirectional data transfer between the PIC and external devices, such as other microcontrollers or personal computers....
, and EthernetMicrochip Product Selectorhttp://www.microchip.com/productselector/MCUProductSelector.html
Limitations
The PIC architectures have these limitations:- One accumulatorAccumulator (computing)In a computer's central processing unit , an accumulator is a register in which intermediate arithmetic and logic results are stored. Without a register like an accumulator, it would be necessary to write the result of each calculation to main memory, perhaps only to be read right back again for...
- Register-bank switchingBank switchingBank switching is a technique to increase the amount of usable memory beyond the amount directly addressable by the processor. It can be used to configure a system differently at different times; for example, a ROM required to start a system from diskette could be switched out when no longer...
is required to access the entire RAM of many devices - Operations and registers are not orthogonal; some instructions can address RAM and/or immediate constants, while others can only use the accumulator
The following stack limitations have been addressed in the PIC18 series, but still apply to earlier cores:
- The hardware call stack is not addressable, so preemptive task switchingComputer multitaskingIn computing, multitasking is a method where multiple tasks, also known as processes, share common processing resources such as a CPU. In the case of a computer with a single CPU, only one task is said to be running at any point in time, meaning that the CPU is actively executing instructions for...
cannot be implemented - Software-implemented stackStack (data structure)In computer science, a stack is a last in, first out abstract data type and linear data structure. A stack can have any abstract data type as an element, but is characterized by only three fundamental operations: push, pop and stack top. The push operation adds a new item to the top of the stack,...
s are not efficient, so it is difficult to generate reentrant code and support local variableLocal variableIn computer science, a local variable is a variable that is given local scope. Such a variable is accessible only from the function or block in which it is declared. In programming languages with only two levels of visibility, local variables are contrasted with global variables...
s
With paged program memory, there are two page sizes to worry about: one for CALL and GOTO and another for computed GOTO (typically used for table lookups). For example, on PIC16, CALL and GOTO have 11 bits of addressing, so the page size is 2048 instruction words. For computed GOTOs, where you add to PCL, the page size is 256 instruction words. In both cases, the upper address bits are provided by the PCLATH register. This register must be changed every time control transfers between pages. PCLATH must also be preserved by any interrupt handler.
Compiler development
While several commercial compilers are available, in 2008, Microchip released their own C compilers, C18 and C30, for the line of 18F 24F and 30/33F processors.The easy to learn RISC instruction set of the PIC assembly language code can make the overall flow difficult to comprehend. Judicious use of simple macros can increase the readability of PIC assembly language. For example, the original Parallax
Parallax, Inc. (company)
Parallax Inc. is a privately held company in Rocklin, California. Parallax Inc. designs, manufactures, and sells BASIC Stamp microcontrollers, Propeller microcontrollers, microcontroller accessories Parallax Inc. is a privately held company in Rocklin, California. Parallax Inc. designs,...
PIC assembler ("SPASM") has macros which hide W and make the PIC look like a two-address machine. It has macro instructions like "
mov b, a" (move the data from address a to address b) and "add b, a" (add data from address a to data in address b). It also hides the skip instructions by providing three operand branch macro instructions such as "cjne a, b, dest" (compare a with b and jump to dest if they are not equal).Baseline core devices
These devices feature a 12-bit wide code memory, a 32-byte register file, and a tiny two level deep call stack. They are represented by the PIC10 series, as well as by some PIC12 and PIC16 devices. Baseline devices are available in 6-pin to 40-pin packages.Generally the first 7 to 9 bytes of the register file are special-purpose registers, and the remaining bytes are general purpose RAM. Pointers are implemented using a register pair: after writing an address to the FSR (file select register), the INDF (indirect f) register becomes an alias for the addressed register.
If banked RAM is implemented, the bank number is selected by the high 3 bits of the FSR. This affects register numbers 16–31; registers 0–15 are global and not affected by the bank select bits.
Because of the very limited register space (5 bits), 4 rarely-read registers were not assigned addresses, but written by special instructions (
OPTION and TRIS).The ROM address space is 512 words (12 bits each), which may be extended to 2048 words by banking.
CALL and GOTO instructions specify the low 9 bits of the new code location; additional high-order bits are taken from the status register. Note that a CALL instruction only includes 8 bits of address, and may only specify addresses in the first half of each 512-word page.Lookup tables are implemented using a computed
GOTO (assignment to PCL register) into a table of RETLW instructions.The instruction set is as follows. Register numbers are referred to as "f", while constants are referred to as "k". Bit numbers (0–7) are selected by "b". The "d" bit selects the destination: 0 indicates W, while 1 indicates that the result is written back to source register f. The C and Z status flags may be set based on the result; otherwise they are unmodified. Add and subtract (but not rotate) instructions that set C also set the DC (digit carry) flag, the carry from bit 3 to bit 4, which is useful for BCD
Binary-coded decimal
In computing and electronic systems, binary-coded decimal is a digital encoding method for numbers using decimal notation, with each decimal digit represented by its own binary sequence. In BCD, a numeral is usually represented by four bits which, in general, represent the decimal range 0 through 9...
arithmetic.
| 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | Mnemonic | C? | Z? | Description |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | opcode | Miscellaneous instructions | |||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | NOP | No operation (MOVW 0,W) | ||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | OPTION | Copy W to OPTION register | ||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | SLEEP | Go into standby mode | ||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CLRWDT | Restart watchdog timer | ||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | f | TRIS f | Copy W to tri-state register (f = 1, 2 or 3) | |||
| 0 | 0 | opcode | d | register | ALU operations: dest ← OP(f,W) | ||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | f | MOVWF f | dest ← W | ||||||
| 0 | 0 | 0 | 0 | 0 | 1 | d | f | CLR f,d | Z | dest ← 0, usually written CLRW or CLRF f | |||||
| 0 | 0 | 0 | 0 | 1 | 0 | d | f | SUBWF f,d | C | Z | dest ← f−W | ||||
| 0 | 0 | 0 | 0 | 1 | 1 | d | f | DECF f,d | Z | dest ← f−1 | |||||
| 0 | 0 | 0 | 1 | 0 | 0 | d | f | IORWF f,d | Z | dest ← f|W, logical inclusive or | |||||
| 0 | 0 | 0 | 1 | 0 | 1 | d | f | ANDWF f,d | Z | dest ← f&W, logical and | |||||
| 0 | 0 | 0 | 1 | 1 | 0 | d | f | XORWF f,d | Z | dest ← f^W, logical exclusive or | |||||
| 0 | 0 | 0 | 1 | 1 | 1 | d | f | ADDWF f,d | C | Z | dest ← f+W | ||||
| 0 | 0 | 1 | 0 | 0 | 0 | d | f | MOVF f,d | Z | dest ← f | |||||
| 0 | 0 | 1 | 0 | 0 | 1 | d | f | COMF f,d | Z | dest ← ~f, bitwise complement | |||||
| 0 | 0 | 1 | 0 | 1 | 0 | d | f | INCF f,d | Z | dest ← f+1 | |||||
| 0 | 0 | 1 | 0 | 1 | 1 | d | f | DECFSZ f,d | dest ← f−1, then skip if zero | ||||||
| 0 | 0 | 1 | 1 | 0 | 0 | d | f | RRF f,d | C | dest ← CARRY*128 | f>>1, rotate right through carry | |||||
| 0 | 0 | 1 | 1 | 0 | 1 | d | f | RLF f,d | C | dest ← F<<1 | CARRY, rotate left through carry | |||||
| 0 | 0 | 1 | 1 | 1 | 0 | d | f | SWAPF f,d | dest ← f<<4 | f>>4, swap nibbles | ||||||
| 0 | 0 | 1 | 1 | 1 | 1 | d | f | INCFSZ f,d | dest ← f+1, then skip if zero | ||||||
| 0 | 1 | op | bit | register | Bit operations | ||||||||||
| 0 | 1 | 0 | 0 | bit | f | BCF f,b | Clear bit b of f | ||||||||
| 0 | 1 | 0 | 1 | bit | f | BSF f,b | Set bit b of f | ||||||||
| 0 | 1 | 1 | 0 | bit | f | BTFSC f,b | Skip if bit b of f is clear | ||||||||
| 0 | 1 | 1 | 1 | bit | f | BTFSS f,b | Skip if bit b of f is set | ||||||||
| 1 | 0 | op | k | Control transfers | |||||||||||
| 1 | 0 | 0 | 0 | k | RETLW k | Set W ← k, then return from subroutine | |||||||||
| 1 | 0 | 0 | 1 | k | CALL k | Call subroutine, 8-bit address k | |||||||||
| 1 | 0 | 1 | k | GOTO k | Jump to 9-bit address k | ||||||||||
| 1 | 1 | op | 8-bit immediate | Operations with W and 8-bit literal: W ← OP(k,W) | |||||||||||
| 1 | 1 | 0 | 0 | k | MOVLW k | W ← k | |||||||||
| 1 | 1 | 0 | 1 | k | IORLW k | Z | W ← k|W, bitwise logical or | ||||||||
| 1 | 1 | 1 | 0 | k | ANDLW k | Z | W ← k&W, bitwise and | ||||||||
| 1 | 1 | 1 | 1 | k | XORLW k | Z | W ← k^W, bitwise exclusive or | ||||||||
| 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | Mnemonic | C? | Z? | Description |
Mid-range core devices
These devices feature a 14-bit wide code memory, and an improved 8 level deep call stack. The instruction set differs very little from the baseline devices, but the increased opcode width allows 128 registers and 2048 words of code to be directly addressed. The mid-range core is available in the majority of devices labeled PIC12 and PIC16.The first 32 bytes of the register space are allocated to special-purpose registers; the remaining 96 bytes are used for general-purpose RAM. If banked RAM is used, the high 16 registers (0x70–0x7F) are global, as are a few of the most important special-purpose registers, including the STATUS register which holds the RAM bank select bits. (The other global registers are FSR and INDF, the low 8 bits of the program counter PCL, the PC high preload register PCLATH, and the master interrupt control register INTCON.)
The PCLATH register supplies high-order instruction address bits when the 8 bits supplied by a write to the PCL register, or the 11 bits supplied by a
GOTO or CALL instruction, is not sufficient to address the available ROM space.
| 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | Mnemonic | C? | Z? | Description |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | opcode | Miscellaneous instructions | |||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | NOP | No operation (MOVW 0,W) | ||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | RETURN | Return from subroutine, W unmodified | ||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | RETFIE | Return from interrupt | ||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | OPTION | Copy W to OPTION register | ||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | SLEEP | Go into standby mode | ||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | CLRWDT | Restart watchdog timer | ||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | f | TRIS f | Copy W to tri-state register (f = 1, 2 or 3) | |||
| 0 | 0 | opcode | d | register | ALU operations: dest ← OP(f,W) | ||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | f | MOVWF f | f ← W | ||||||||
| 0 | 0 | 0 | 0 | 0 | 1 | d | f | CLR f,d | Z | dest ← 0, usually written CLRW or CLRF f | |||||||
| 0 | 0 | 0 | 0 | 1 | 0 | d | f | SUBWF f,d | C | Z | dest ← f−W | ||||||
| 0 | 0 | 0 | 0 | 1 | 1 | d | f | DECF f,d | Z | dest ← f−1 | |||||||
| 0 | 0 | 0 | 1 | 0 | 0 | d | f | IORWF f,d | Z | dest ← f|W, logical inclusive or | |||||||
| 0 | 0 | 0 | 1 | 0 | 1 | d | f | ANDWF f,d | Z | dest ← f&W, logical and | |||||||
| 0 | 0 | 0 | 1 | 1 | 0 | d | f | XORWF f,d | Z | dest ← f^W, logical exclusive or | |||||||
| 0 | 0 | 0 | 1 | 1 | 1 | d | f | ADDWF f,d | C | Z | dest ← f+W | ||||||
| 0 | 0 | 1 | 0 | 0 | 0 | d | f | MOVF f,d | Z | dest ← f | |||||||
| 0 | 0 | 1 | 0 | 0 | 1 | d | f | COMF f,d | Z | dest ← ~f, bitwise complement | |||||||
| 0 | 0 | 1 | 0 | 1 | 0 | d | f | INCF f,d | Z | dest ← f+1 | |||||||
| 0 | 0 | 1 | 0 | 1 | 1 | d | f | DECFSZ f,d | dest ← f−1, then skip if zero | ||||||||
| 0 | 0 | 1 | 1 | 0 | 0 | d | f | RRF f,d | C | dest ← CARRY*128 | f>>1, rotate right through carry | |||||||
| 0 | 0 | 1 | 1 | 0 | 1 | d | f | RLF f,d | C | dest ← f<<1 | CARRY, rotate left through carry | |||||||
| 0 | 0 | 1 | 1 | 1 | 0 | d | f | SWAPF f,d | dest ← f<<4 | f>>4, swap nibbles | ||||||||
| 0 | 0 | 1 | 1 | 1 | 1 | d | f | INCFSZ f,d | dest ← f+1, then skip if zero | ||||||||
| 0 | 1 | op | bit | register | Bit operations | ||||||||||||
| 0 | 1 | 0 | 0 | bit | f | BCF f,b | Clear bit b of f | ||||||||||
| 0 | 1 | 0 | 1 | bit | f | BSF f,b | Set bit b of f | ||||||||||
| 0 | 1 | 1 | 0 | bit | f | BTFSC f,b | Skip if bit b of f is clear | ||||||||||
| 0 | 1 | 1 | 1 | bit | f | BTFSS f,b | Skip if bit b of f is set | ||||||||||
| 1 | 0 | op | k | Control transfers | |||||||||||||
| 1 | 0 | 0 | k | CALL k | Call subroutine | ||||||||||||
| 1 | 0 | 1 | k | GOTO k | Jump to address k | ||||||||||||
| 1 | 1 | op | 8-bit immediate | Operations with W and 8-bit literal: W ← OP(k,W) | |||||||||||||
| 1 | 1 | 0 | 0 | x | x | k | MOVLW k | W ← k | |||||||||
| 1 | 1 | 0 | 1 | x | x | k | RETLW k | W ← k, then return from subroutine | |||||||||
| 1 | 1 | 1 | 0 | 0 | 0 | k | IORLW k | Z | W ← k|W, bitwise logical or | ||||||||
| 1 | 1 | 1 | 0 | 0 | 1 | k | ANDLW k | Z | W ← k&W, bitwise and | ||||||||
| 1 | 1 | 1 | 0 | 1 | 0 | k | XORLW k | Z | W ← k^W, bitwise exclusive or | ||||||||
| 1 | 1 | 1 | 0 | 1 | 1 | k | (reserved) | ||||||||||
| 1 | 1 | 1 | 1 | 0 | x | k | SUBLW k | C | Z | W ← k−W, subtract | |||||||
| 1 | 1 | 1 | 1 | 1 | x | k | ADDLW k | C | Z | W ← k+W, add | |||||||
| 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | Mnemonic | C? | Z? | Description |
Enhanced Mid-range core devices
Enhanced Mid-range core devices introduce a deeper hardware stack, additional reset methods, 14 additional instructions and ‘C’ programming language optimizations. In particular. there are twoINDF registers (INDF0 and INDF1), and two corresponding FSR register pairs (FSRnL and FSRnH). Special instructions use FSRn registers like address registers, with a variety of addressing modeAddressing modeAddressing modes are an aspect of the instruction set architecture in most central processing unit designs. The various addressing modes that are defined in a given instruction set architecture define how machine language instructions in that architecture identify the operand of each instruction...
s.
14-bit enhanced PIC additional instructions
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Mnemonic
C?
Z?
Description
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opcode
Miscellaneous instructions
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RESET
Software reset
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CALLW
Push PC, then jump to PCLATH:W
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BRW
PC ← PC + W, relative jump using W
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MOVIW ++FSRn
Z
Increment FSRn, then W ← INDFn
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MOVIW −−FSRn
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Decrement FSRn, then W ← INDFn
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MOVIW FSRn++
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W ← INDFn, then increment FSRn
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MOVIW FSRn−−
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W ← INDFn, then decrement FSRn
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m
MOVWI using FSRn
INDFn ← W, same modes as MOVIW
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k
MOVLB k
BSR ← k, move literal to bank select register
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opcode
d
register
ALU operations: dest ← OP(f,W)
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LSLF f,d
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dest ← f << 1, logical shift left
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LSRF f,d
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Z
dest ← f >> 1, logical shift right
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ASRF f,d
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Z
dest ← f >> 1, arithmetic shift right
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SUBWFB f,d
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dest ← f − W − 1 + C, subtract with carry
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ADDWFC f,d
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Z
dest ← f + W + C, add with carry
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opcode
k
Operations with literal k
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ADDFSR FSRn,k
FSRn ← FSRn + k, add 6-bit signed offset
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k
MOVLP k
PCLATH ← k, move 7-bit literal to PC latch high
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BRA k
PC ← PC + k, branch relative using 9-bit signed offset
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MOVIW k[FSRn]
Z
W ← [FSRn+k], 6-bit signed offset
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MOVWI k[FSRn]
[FSRn+k] ← W, 6-bit signed offset
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Mnemonic
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Z?
Description
PIC17 high end core devices
The 17 series never became popular and has been superseded by the PIC18 architecture. It is not recommended for new designs, and availability may be limited.
Improvements over earlier cores are 16-bit wide opcodes (allowing many new instructions), and a 16 level deep call stack. PIC17 devices were produced in packages from 40 to 68 pins.
The 17 series introduced a number of important new features:
- a memory mapped accumulator
- read access to code memory (table reads)
- direct register to register moves (prior cores needed to move registers through the accumulator)
- an external program memory interface to expand the code space
- an 8-bit x 8-bit hardware multiplier
- a second indirect register pair
- auto-increment/decrement addressing controlled by control bits in a status register (ALUSTA)
PIC18 high end core devices
Microchip introduced the PIC18 architecture in 2000. http://mdubuc.freeshell.org/Sdcc/ Unlike the 17 series, it has proven to be very popular, with a large number of device variants presently in manufacture. In contrast to earlier devices, which were more often than not programmed in assembly, C has become the predominant development language http://www.microchipc.com/sourcecode/.
The 18 series inherits most of the features and instructions of the 17 series, while adding a number of important new features:
- much deeper call stack (31 levels deep)
- the call stack may be read and written
- conditional branch instructions
- indexed addressing mode (PLUSW)
- extending the FSR registers to 12 bits, allowing them to linearly address the entire data address space
- the addition of another FSR register (bringing the number up to 3)
The auto increment/decrement feature was improved by removing the control bits and adding four new indirect registers per FSR. Depending on which indirect file register is being accessed it is possible to postdecrement, postincrement, or preincrement FSR; or form the effective address by adding W to FSR.
In more advanced PIC18 devices, an "extended mode" is available which makes the addressing even more favorable to compiled code:
- a new offset addressing mode; some addresses which were relative to the access bank are now interpreted relative to the FSR2 register
- the addition of several new instructions, notable for manipulating the FSR registers.
These changes were primarily aimed at improving the efficiency of a data stack implementation. If FSR2 is used either as the stack pointer or frame pointer, stack items may be easily indexed—allowing more efficient re-entrant code. Microchip's MPLAB C18 C compiler chooses to use FSR2 as a frame pointer.
PIC24 and dsPIC 16-bit microcontrollers
In 2001, Microchip introduced the dsPIC series of chips, which entered mass production in late 2004. They are Microchip's first inherently 16-bit microcontrollers. PIC24 devices are designed as general purpose microcontrollers. dsPIC devices include digital signal processingDigital signal processingDigital signal processing is concerned with the representation of discrete time signals by a sequence of numbers or symbols and the processing of these signals. Digital signal processing and analog signal processing are subfields of signal processing...
capabilities in addition.
Architecturally, although they share the PIC moniker, they are very different from the 8-bit PICs. The most notable differences are:
- they feature a set of 16 working registers (W0-W15)
- they fully support a stack in RAM, and do not have a hardware stack
- bank switching is not required to access RAM or special function registers
- data stored in program memory can be accessed directly using a feature called Program Space Visibility
- interrupt sources may be assigned to distinct handlers using an interrupt vector table
Some features are:
- hardware MAC (multiply–accumulate)
- barrel shiftingBarrel shifterA barrel shifter is a digital circuit that can shift a data word by a specified number of bits in one clock cycle. It can be implemented as a sequence of multiplexers , and in such an implementation the output of one mux is connected to the input of the next mux in a way that depends on the shift...
- bit reversal
- (16×16)-bit single-cycle multiplication and other DSP operations
- hardware divide assist (19 cycles for 16/32-bit divide)
- hardware support for loop indexing
- Direct memory accessDirect memory accessDirect memory access is a feature of modern computers that allows certain hardware subsystems within the computer to access system memory independently of the central processing unit ....
dsPICs can be programmed in C using Microchip's C30 compiler which is a variant of gccGNU Compiler CollectionThe GNU Compiler Collection is a compiler system produced by the GNU Project supporting various programming languages. GCC is a key component of the GNU toolchain...
.
PIC32 32-bit microcontrollers
In November 2007 Microchip introduced the new PIC32MX family of 32-bit microcontrollers.
The initial device line-up is based on the industry standard MIPS32 M4K CoreMIPS architectureMIPS is a reduced instruction set computer instruction set architecture developed by MIPS Technologies . The early MIPS architectures were 32-bit, and later versions were 64-bit...
http://www.mips.com/products/processors/32-64-bit-cores/mips32-m4k/. The device can be programmed using the Microchip MPLAB C Compiler for PIC32 MCUs, a variant of the GCC compiler. The first 18 models currently in production (PIC32MX3xx and PIC32MX4xx) are pin to pin compatible and share the same peripherals set with the PIC24FxxGA0xx family of (16-bit) devices allowing the use of common libraries, software and hardware tools.
The PIC32 architecture brings a number of new features to Microchip portfolio, including:
- The highest execution speed 80 MIPS (120+ DhrystoneDhrystoneDhrystone is a synthetic computing benchmark program developed in 1984 by Reinhold P. Weicker intended to be representative of system programming. The Dhrystone grew to become representative of general processor performance...
)
- The largest flash memory:
- One instruction per clock cycle execution
- The first cached processor
- Allows execution from RAM
- Full Speed Host/Dual Role and OTG USB capabilities
- Full JTAG and 2 wire programming and debugging
- Real-time trace
Device variants and hardware features
PIC devices generally feature:
- Sleep mode (power savings).
- Watchdog timerWatchdog timerA watchdog timer is a computer hardware or software timer that triggers a system reset or other corrective action if the main program, due to some fault condition, such as a hang, neglects to regularly service the watchdog A watchdog timer (or computer operating properly (COP) timer) is a computer...
.
- Various crystal or RCRC circuitA resistor–capacitor circuit ', or RC filter or RC network, is an electric circuit composed of resistors and capacitors driven by a voltage or current source...
oscillator configurations, or an external clock.
Variants
Within a series, there are still many device variants depending on what hardware resources the chip features.
- General purpose I/O pinsGPIOGeneral Purpose Input/Output is a generic pin on a chip whose behavior can be controlled through software....
.
- Internal clock oscillators.
- 8/16/32 Bit Timers.
- Internal EEPROMEEPROMEEPROM stands for Electrically Erasable Programmable Read-Only Memory and is a type of non-volatile memory used in computers and other electronic devices to store small amounts of data that must be saved when power is removed, e.g., calibration...
Memory.
- Synchronous/Asynchronous Serial Interface USART.
- MSSP Peripheral for I²CI²CI²C is a multi-master serial single-ended computer bus invented by Philips that is used to attach low-speed peripherals to a motherboard, embedded system, cellphone, or other electronic device. Since the mid 1990s, several competitors I²C ("i-squared cee" or "i-two cee"; Inter-Integrated Circuit;...
and SPI Communications.
- Capture/Compare and PWMPulse-width modulationPulse-width modulation , or pulse-duration modulation , is a commonly used technique for controlling power to inertial electrical devices, made practical by modern electronic power switches....
modules.
- Analog-to-digital converterAnalog-to-digital converterAn analog-to-digital converter is a device that converts a continuous quantity to a discrete time digital representation. An ADC may also provide an isolated measurement...
s (up to ~1.0 MHzHertzThe hertz is the SI unit of frequency defined as the number of cycles per second of a periodic phenomenon. One of its most common uses is the description of the sine wave, particularly those used in radio and audio applications....
).
- USB, EthernetEthernetEthernet is a family of computer networking technologies for local area networks commercially introduced in 1980. Standardized in IEEE 802.3, Ethernet has largely replaced competing wired LAN technologies....
, CANController Area NetworkController–area network is a vehicle bus standard designed to allow microcontrollers and devices to communicate with each other within a vehicle without a host computer....
interfacing support.
- External memory interface.
- Integrated analog RF front ends (PIC16F639, and rfPIC).
- KEELOQKeeLoqKeeLoq is a proprietary hardware-dedicated NLFSR-based block cipher. The uni-directional command transfer protocol was designed by Frederick Bruwer, PhD, CEO at Nanoteq Ltd and the cryptographic algorithm was created by Professor Gideon Kuhn with the silicon implementation by Willem Smit, PhD, at...
Rolling code encryption peripheral (encode/decode)
- And many more.
Trends
The first generation of PICs with EPROMEPROMAn EPROM , or erasable programmable read only memory, is a type of memory chip that retains its data when its power supply is switched off. In other words, it is non-volatile. It is an array of floating-gate transistors individually programmed by an electronic device that supplies higher voltages...
storage are almost completely replaced by chips with Flash memoryFlash memoryFlash memory is a non-volatile computer storage chip that can be electrically erased and reprogrammed. It was developed from EEPROM and must be erased in fairly large blocks before these can be rewritten with new data...
. Likewise, the original 12-bit instruction set of the PIC1650 and its direct descendants has been superseded by 14-bit and 16-bit instruction sets. Microchip still sells OTP (one-time-programmable) and windowed (UV-erasable) versions of some of its EPROM based PICs for legacy support or volume orders. The Microchip website lists PICs that are not electrically erasable as OTP despite the fact that UV erasable windowed versions of these chips can be ordered..
History
The original PIC was built to be used with General Instruments' new 16-bit CPUCentral processing unitThe central processing unit is the portion of a computer system that carries out the instructions of a computer program, to perform the basic arithmetical, logical, and input/output operations of the system. The CPU plays a role somewhat analogous to the brain in the computer. The term has been in...
, the CP1600. While generally a good CPU, the CP1600 had poor I/OInput/outputIn computing, input/output, or I/O, refers to the communication between an information processing system , and the outside world, possibly a human, or another information processing system. Inputs are the signals or data received by the system, and outputs are the signals or data sent from it...
performance, and the 8-bit PIC was developed in 1975 to improve performance of the overall system by offloading I/O tasks from the CPU. The PIC used simple microcodeMicrocodeMicrocode is a layer of hardware-level instructions and/or data structures involved in the implementation of higher level machine code instructions in many computers and other processors; it resides in special high-speed memory and translates machine instructions into sequences of detailed...
stored in ROM to perform its tasks, and although the term was not used at the time, it shares some common features with RISCReduced instruction set computerReduced instruction set computing, or RISC , is a CPU design strategy based on the insight that simplified instructions can provide higher performance if this simplicity enables much faster execution of each instruction. A computer based on this strategy is a reduced instruction set computer...
designs.
In 1985, General Instruments spun off their microelectronicsMicroelectronicsMicroelectronics is a subfield of electronics. As the name suggests, microelectronics relates to the study and manufacture of very small electronic components. Usually, but not always, this means micrometre-scale or smaller,. These devices are made from semiconductors...
division and the new ownership cancelled almost everything — which by this time was mostly out-of-date. The PIC, however, was upgraded with internal EPROMEPROMAn EPROM , or erasable programmable read only memory, is a type of memory chip that retains its data when its power supply is switched off. In other words, it is non-volatile. It is an array of floating-gate transistors individually programmed by an electronic device that supplies higher voltages...
to produce a programmable channel controller and today a huge variety of PICs are available with various on-board peripherals (serial communicationSerial communicationsIn telecommunication and computer science, serial communication is the process of sending data one bit at a time, sequentially, over a communication channel or computer bus. This is in contrast to parallel communication, where several bits are sent as a whole, on a link with several parallel channels...
modules, UARTUniversal asynchronous receiver/transmitterA universal asynchronous receiver/transmitter, abbreviated UART , is a type of "asynchronous receiver/transmitter", a piece of computer hardware that translates data between parallel and serial forms. UARTs are commonly used in conjunction with communication standards such as EIA RS-232, RS-422 or...
s, motor control kernels, etc.) and program memory from 256 words to 64k words and more (a "word" is one assembly language instruction, varying from 12, 14 or 16 bitBitA bit is the basic unit of information in computing and telecommunications; it is the amount of information stored by a digital device or other physical system that exists in one of two possible distinct states...
s depending on the specific PIC microMicro programming languageThe Micro programming language is a very basic programming language used in teaching computer science students principles of compiler construction.The language itself is built on top of an even more basic language called Tiny, which is also used in compiler construction courses...
family).
PIC and PICmicro are registered trademarks of Microchip Technology. It is generally thought that PIC stands for Peripheral Interface Controller, although General Instruments' original acronym for the initial PIC1640 and PIC1650 devices was "Programmable Interface Controller". The acronym was quickly replaced with "Programmable Intelligent Computer".
The Microchip 16C84 (PIC16x84PIC16x84The PIC16C84, PIC16F84 and PIC16F84A are microcontrollers in the PIC family of controllers, produced by Microchip Technology.- Description :The PIC16x84 is a microcontroller in the PIC family of controllers produced by Microchip Technology....
), introduced in 1993 ,
was the first Microchip CPU with on-chip EEPROM memory.
This electrically erasable memory made it cost less than CPUs that required a quartz "erase window" for erasing EPROM.
Development tools
Microchip provides a freewareFreewareFreeware is computer software that is available for use at no cost or for an optional fee, but usually with one or more restricted usage rights. Freeware is in contrast to commercial software, which is typically sold for profit, but might be distributed for a business or commercial purpose in the...
IDEIntegrated development environmentAn integrated development environment is a software application that provides comprehensive facilities to computer programmers for software development...
package called MPLABMPLABMPLAB Integrated Development Environment is a free, integrated toolset for the development of embedded applications on Microchip's PIC and dsPIC microcontrollers.- MPLAB IDE v8 :...
, which includes an assembler, linker, software simulator, and debugger. They also sell C compilers for the PIC18 and dsPIC which integrate cleanly with MPLAB. Free student versions of the C compilers are also available with all features. But for the free versions, optimizations will be disabled after 60 days.
Several third parties make CC (programming language)C is a general-purpose computer programming language developed between 1969 and 1973 by Dennis Ritchie at the Bell Telephone Laboratories for use with the Unix operating system....
language compilers for PICs, many of which integrate to MPLAB and/or feature their own IDE. A fully featured compiler for the PICBASIC language to program PIC microcontrollers is available from meLabs, Inc.
Development tools are available for the PIC family under the GPL or other free software or open sources licenses.
Device programmers
Devices called "programmerProgrammer (hardware)In field of computer hardware, the term programmer, chip programmer or device programmer refers to a hardware device that configures programmable non-volatile circuits such as EPROMs, EEPROMs, Flashs, PALs, FPGAs or programmable logic circuits....
s" are traditionally used to get program code into the target PIC. Most PICs that Microchip currently sell feature ICSPIn Circuit Serial Programming (ICSP)In Circuit Serial Programming is a method of directly programming AVRs, the Parallax Propeller, and PIC microcontrollers.-See also:*In-system programming*Device Programmers...
(In Circuit Serial Programming) and/or LVP (Low Voltage Programming) capabilities, allowing the PIC to be programmed while it is sitting in the target circuitElectronic circuitAn electronic circuit is composed of individual electronic components, such as resistors, transistors, capacitors, inductors and diodes, connected by conductive wires or traces through which electric current can flow...
. ICSP programming is performed using two pins, clock and data, while a high voltage (12V) is present on the Vpp/MCLR pin. Low voltage programming dispenses with the high voltage, but reserves exclusive use of an I/O pin and can therefore be disabled to recover the pin for other uses (once disabled it can only be re-enabled using high voltage programming).
There are many programmers for PIC microcontrollers, ranging from the extremely simple designs which rely on ICSP to allow direct download of code from a host computer, to intelligent programmers that can verify the device at several supply voltages. Many of these complex programmers use a pre-programmed PIC themselves to send the programming commands to the PIC that is to be programmed. The intelligent type of programmer is needed to program earlier PIC models (mostly EPROM type) which do not support in-circuit programming.
Many of the higher end flash based PICs can also self-program (write to their own program memory). Demo boards are available with a small bootloader factory programmed that can be used to load user programs over an interface such as RS-232RS-232In telecommunications, RS-232 is the traditional name for a series of standards for serial binary single-ended data and control signals connecting between a DTE and a DCE . It is commonly used in computer serial ports...
or USBUniversal Serial BusUSB is an industry standard developed in the mid-1990s that defines the cables, connectors and protocols used in a bus for connection, communication and power supply between computers and electronic devices....
, thus obviating the need for a programmer device. Alternatively there is bootloader firmware available that the user can load onto the PIC using ICSP. The advantages of a bootloader over ICSP is the far superior programming speeds, immediate program execution following programming, and the ability to both debug and program using the same cable.
Programmers/debuggers are available directly from Microchip. Third party programmers range from plans to build your own, to self-assembly kits and fully tested ready-to-go units. Some are simple designs which require a PC to do the low-level programming signalling (these typically connect to the serialSerial portIn computing, a serial port is a serial communication physical interface through which information transfers in or out one bit at a time...
or parallel portParallel portA parallel port is a type of interface found on computers for connecting various peripherals. In computing, a parallel port is a parallel communication physical interface. It is also known as a printer port or Centronics port...
and consist of a few simple components), while others have the programming logic built into them (these typically use a serial or USB connection, are usually faster, and are often built using PICs themselves for control).
In-circuit debugging
Later model PICs feature an ICD (in-circuit debugging) interface, built into the CPU core. ICD debuggers (MPLAB ICD2 and other third party) can communicate with this interface using three lines. This cheap and simple debugging system comes at a price however, namely limited breakpoint count (1 on older pics 3 on newer PICs), loss of some IO (with the exception of some surface mount 44-pin PICs which have dedicated lines for debugging) and loss of some features of the chip. For small PICs, where the loss of IO caused by this method would be unacceptable, special headers are made which are fitted with PICs that have extra pins specifically for debugging.
In-circuit emulators
Microchip offers three full in circuit emulators: the MPLAB ICE2000 (parallel interface, a USB converter is available); the newer MPLAB ICE4000 (USB 2.0 connection); and most recently, the REAL ICE. All of these ICE tools can be used with the MPLAB IDE for full source-level debugging of code running on the target.
The ICE2000 requires emulator modules, and the test hardware must provide a socket which can take either an emulator module, or a production device.
The REAL ICE connects directly to production devices which support in-circuit emulation through the PGC/PGD programming interface, or through a high speed connection which uses two more pins. According to Microchip, it supports "most" flash-based PIC, PIC24, and dsPIC processors.
The ICE4000 is no longer directly advertised on Microchip's website, and the purchasing page states that it is not recommended for new designs.
PICKit 2 open source structure and clones
PICKit 2 has been an interesting PIC programmer from Microchip. It can program all PICs and debug most of the PICs (as of May-2009, only the PIC32 family is not supported for MPLAB debugging). Ever since its first releases, all software source code (firmware, PC application) and hardware schematic are open to the public. This makes it relatively easy for an end user to modify the programmer for use with a non-Windows operating system such as Linux or Mac OS. In the mean time, it also creates lots of DIY interest and clones. This open source structure brings many features to the PICKit 2 community such as Programmer-to-Go, the UART Tool and the Logic Tool, which have been contributed by PICKit 2 users. Users have also added such features to the PICKit 2 as 4MB Programmer-to-go capability, USB buck/boost circuits, RJ12 type connectors and others.
Part number suffixes
The F in a name generally indicates the PICmicro uses flash memory and can be erased electronically. A C generally means it can only be erased by exposing the die to ultraviolet light (which is only possible if a windowed package style is used). An exception to this rule is the PIC16C84 which uses EEPROM and is therefore electrically erasable.
An L in the name indicates the part will run at a lower voltage, often with frequency limits imposed.
Parts designed specifically for low voltage operation, within a strict range of 3 - 3.6 Volts, are marked with a J in the part number. These parts are also uniquely I/O tolerant as they will accept up to 5V as inputs.
See also
- PIC16x84PIC16x84The PIC16C84, PIC16F84 and PIC16F84A are microcontrollers in the PIC family of controllers, produced by Microchip Technology.- Description :The PIC16x84 is a microcontroller in the PIC family of controllers produced by Microchip Technology....
- Atmel AVRAtmel AVRThe AVR is a modified Harvard architecture 8-bit RISC single chip microcontroller which was developed by Atmel in 1996. The AVR was one of the first microcontroller families to use on-chip flash memory for program storage, as opposed to one-time programmable ROM, EPROM, or EEPROM used by other...
- ArduinoArduinoArduino is an open-source single-board microcontroller, descendant of the open-source Wiring platform, designed to make the process of using electronics in multidisciplinary projects more accessible. The hardware consists of a simple open hardware design for the Arduino board with an Atmel AVR...
- BASIC AtomBASIC AtomBasic Atom refers to a line of products from .Like the Basic stamp, the Basic Atom line is based upon various microchips pre-programmed with an interpreter, making it easy to change "programs", as they are only "data" being interpreted...
- BASIC StampBASIC StampThe BASIC Stamp is a microcontroller with a small, specialized BASIC interpreter built into ROM. It is made by Parallax, Inc. and has been popular with electronics hobbyists since the early 1990s because of its low threshold of learning and ease of use due to its simple to understand BASIC...
- Dwengo
- OOPicOOPicThe OOPic is an Object Oriented Programmable Integrated Circuit. Created by Savage Innovations, this PIC microcontroller comes with an IDE that supports programming in syntaxes based on the BASIC, Java and C programming languages.There are three versions currently on the market: the , the and the...
- PICAXEPICAXEPICAXE is the name of a UK-sourced microcontroller system based on a range of Microchip PICs. There are 13 PICAXE variants of differing pin counts from 8 to 40 pins. Initially marketed for use in education and by electronics hobbyists, they are also used in commercial and technical fields,...
- TI MSP430TI MSP430The MSP430 is a mixed-signal microcontroller family from Texas Instruments. Built around a 16-bit CPU, the MSP430 is designed for low cost, and specifically, low power consumption embedded applications. The architecture dates from the 1990s and is reminiscent of the DEC PDP-11.-Applications:The...
- MaximiteMaximiteMaximite Microcomputer is a Microchip PIC32 Microcontroller based Microcomputer. Originally designed as a hobby kit described by Australian Designer Geoff Graham in a 3 part article ....
External links
.