Memory timings refer collectively to a set of four numerical parameters called CL, tRCD, tRP, and tRAS, commonly represented as a series of four numbers separated with dashes, in that respective order (e.g. 5-5-5-15). However, it is not unusual for tRAS to be omitted, or for a fifth value, the Command rate, to be added on. It also remains a common practice to advertise only CL. These parameters define, in clock cycles, the various forms of latency (responsiveness to random requests) that affect fundamental performance metrics of random access memory. Lower numbers indicate fewer clock cycles are needed, implying faster performance.

Modern DIMM

DIMM

A DIMM or dual in-line memory module, comprises a series of dynamic random-access memory integrated circuits. These modules are mounted on a printed circuit board and designed for use in personal computers, workstations and servers...

s include a Serial Presence Detect

Serial Presence Detect

Serial presence detect refers to a standardized way to automatically access information about a computer memory module. Earlier 72-pin SIMMs included 5 pins which provided 5 bits of parallel presence detect data, but the 168-pin DIMM standard changed to a serial presence detect to encode much...

 (SPD) ROM chip that contains recommended memory timings for automatic configuration. The BIOS on a PC may allow the user to make adjustments in an effort to increase performance (with possible risk of decreased stability) or, in some cases, to increase stability (by lowering performance).

Memory timings are distinct from memory bandwidth

Memory bandwidth

Memory bandwidth is the rate at which data can be read from or stored into a semiconductor memory by a processor. Memory bandwidth is usually expressed in units of bytes/second, though this can vary for systems with natural data sizes that are not a multiple of the commonly used 8-bit bytes.Memory...

; the latter measures the throughput of memory. It is possible for an advance in memory technology to increase both bandwidth (an apparent performance improvement) and latency (an apparent performance degradation). For example, DDR memory

DDR SDRAM

Double data rate synchronous dynamic random access memory is a class of memory integrated circuits used in computers. DDR SDRAM has been superseded by DDR2 SDRAM and DDR3 SDRAM, neither of which are either forward or backward compatible with DDR SDRAM, meaning that DDR2 or DDR3 memory modules...

 has been superseded by DDR2

DDR2 SDRAM

DDR2 SDRAM is a double data rate synchronous dynamic random-access memory interface. It supersedes the original DDR SDRAM specification and has itself been superseded by DDR3 SDRAM...

, and yet DDR2 has significantly higher latency at the same clock frequencies. However, DDR2 can be clocked faster, decreasing its cycle time; DDR2 clocked significantly higher than DDR also has lower latency (in nanoseconds) than DDR. Increasing memory bandwidth, even while increasing memory latency, can improve the performance of a computer system with multiple processors, and also systems with processors that have multiple execution threads.

Name	Symbol	Definition
CAS latency CAS Latency Column Address Strobe latency, or CL, is the delay time between the moment a memory controller tells the memory module to access a particular memory column on a RAM memory module, and the moment the data from given array location is available on the module's output pins...	CL	The time between sending a column address to the memory and the beginning of the data in response. This is the time it takes to read the first bit of memory from a DRAM with the correct row already open.
Row Address to Column Address Delay	TRCD	The number of clock cycles required between the opening of a row of memory and accessing columns within it. The time to read the first bit of memory from a DRAM without an active row is TRCD + CL.
Row Precharge Time	TRP	The number of clock cycles required between the issuing of the precharge command and opening the next row. The time to read the first bit of memory from a DRAM with the wrong row open is TRP + TRCD + CL.
Row Active Time	TRAS	The number of clock cycles required between a bank active command and issuing the precharge command. This is the time needed to internally refresh the row, and overlaps with TRCD. In SDRAM modules, it is simply TRCD + CL. Otherwise, approximately equal to TRCD + (2 * CL).
Notes: RAS : Row Address Strobe CAS : Column Address Strobe TWR : Write Recovery Time, the time that must elapse between the last write command to a row and precharging it. Generally, TRAS = TRCD + TWR. TRC : Row Cycle Time. TRC = TRAS + TRP.