LARC
Encyclopedia
The UNIVAC
LARC (Livermore Advanced Research Computer) was Remington Rand's first attempt at building a supercomputer
. It was designed for multiprocessing
with 2 CPUs
(called Computers) and an Input/output
(I/O) Processor (called the Processor).
Only two LARCs were built:
However both machines only had one Computer, so no multiprocessor LARCs were ever built.
The LARC was a decimal mainframe computer with 48 bit
s per word. It used bi-quinary coded decimal
arithmetic with 4 bits per digit
, allowing 11-digit signed numbers
. Instructions
were 48 bits long, one per word. Every digit in the machine had one parity bit, for error checking, meaning every word occupied 60 bits (48 bits for data with 12 bits for parity check). The basic configuration had 26 general purpose registers
and could be expanded to 99 general purpose registers. The general purpose registers had an access time of one microsecond.
The basic configuration had one Computer and could be expanded to a multiprocessor with a second Computer.
The Processor is an independent CPU (with a different instruction set from the Computers) and provides control for 12 to 24 Magnetic drum storage units, four to forty UNISERVO II tape drives, two Electronic page recorders, one or two High-speed printers, and a High-speed punched card reader.
The LARC used core memory banks of 2500 words each, housed four banks per memory cabinet. The basic configuration had eight banks of core (two cabinets), 20000 words. The memory could be expanded to a maximum of 39 banks of core (ten cabinets with one empty bank), 97500 words. The core memory had one parity bit on each digit, for error checking, resulting in 60 bits per memory word. The core memory had an access time of 8 microseconds and a cycle time of 4 microseconds. Each bank operated independently and could begin a new access in any 4 microsecond cycle when it was not already busy. By properly interleaving accesses to different banks the memory could sustain an effective access time of 4 microseconds on each access (e.g., instruction access in one bank data in another).
The data transfer bus connecting the two Computers and the Processor to the core memory was multiplexed to maximize throughput; every 4 microsecond bus cycle was divided into eight 500 nanosecond time slots:
The core memory system enforces a system of interlocks and priorities to avoid simultaneous access of the same memory bank by multiple sections of the system (the Computers, Processor, and I/O DMA Synchronizers) without conflicts or deadlocks. A memory bank is unavailable for one 4 microsecond cycle after being addressed by any section of the system. If another section attempts to address the same memory bank during this time it is locked out and must wait then try again in the next 4 microsecond cycle. To prevent deadlocks and timeouts in the I/O system the following priorities are enforced:
If a higher priority section is locked out in one 4 microsecond cycle, when it tries again in the next 4 microsecond cycle, all lower priority sections are prevented from beginning a new cycle on that memory bank until the higher priority section has completed its access.
The LARC was built using surface barrier transistors, which were already obsolete by the time the first system was delivered. The LARC was a very fast computer for its time. Its addition time was 4 microseconds, multiplication time was 8 microseconds, and the division time was 28 microseconds. It was the fastest computer in 1960-1961, until the IBM 7030
took the title.
UNIVAC
UNIVAC is the name of a business unit and division of the Remington Rand company formed by the 1950 purchase of the Eckert-Mauchly Computer Corporation, founded four years earlier by ENIAC inventors J. Presper Eckert and John Mauchly, and the associated line of computers which continues to this day...
LARC (Livermore Advanced Research Computer) was Remington Rand's first attempt at building a supercomputer
Supercomputer
A supercomputer is a computer at the frontline of current processing capacity, particularly speed of calculation.Supercomputers are used for highly calculation-intensive tasks such as problems including quantum physics, weather forecasting, climate research, molecular modeling A supercomputer is a...
. It was designed for multiprocessing
Multiprocessing
Multiprocessing is the use of two or more central processing units within a single computer system. The term also refers to the ability of a system to support more than one processor and/or the ability to allocate tasks between them...
with 2 CPUs
Central processing unit
The central processing unit is the portion of a computer system that carries out the instructions of a computer program, to perform the basic arithmetical, logical, and input/output operations of the system. The CPU plays a role somewhat analogous to the brain in the computer. The term has been in...
(called Computers) and an Input/output
Input/output
In computing, input/output, or I/O, refers to the communication between an information processing system , and the outside world, possibly a human, or another information processing system. Inputs are the signals or data received by the system, and outputs are the signals or data sent from it...
(I/O) Processor (called the Processor).
Only two LARCs were built:
- The first was delivered to LivermoreLawrence Livermore National LaboratoryThe Lawrence Livermore National Laboratory , just outside Livermore, California, is a Federally Funded Research and Development Center founded by the University of California in 1952...
in June 1960. - The second was delivered to the Navy's David Taylor Model BasinDavid Taylor Model BasinThe David Taylor Model Basin is one of the largest ship model basins — test facilities for the development of ship design — in the world...
.
However both machines only had one Computer, so no multiprocessor LARCs were ever built.
The LARC was a decimal mainframe computer with 48 bit
Bit
A bit is the basic unit of information in computing and telecommunications; it is the amount of information stored by a digital device or other physical system that exists in one of two possible distinct states...
s per word. It used bi-quinary coded decimal
Bi-quinary coded decimal
Bi-quinary coded decimal is a numeral encoding scheme used in many abacuses and in some early computers, including the Colossus. The term bi-quinary indicates that the code comprises both a two-state and a five-state component...
arithmetic with 4 bits per digit
Numerical digit
A digit is a symbol used in combinations to represent numbers in positional numeral systems. The name "digit" comes from the fact that the 10 digits of the hands correspond to the 10 symbols of the common base 10 number system, i.e...
, allowing 11-digit signed numbers
Signedness
In computing, signedness is a property of data types representing numbers in computer programs. A numeric variable is signed if it can represent both positive and negative numbers, and unsigned if it can only represent non-negative numbers .As signed numbers can represent negative numbers, they...
. Instructions
Instruction set
An instruction set, or instruction set architecture , is the part of the computer architecture related to programming, including the native data types, instructions, registers, addressing modes, memory architecture, interrupt and exception handling, and external I/O...
were 48 bits long, one per word. Every digit in the machine had one parity bit, for error checking, meaning every word occupied 60 bits (48 bits for data with 12 bits for parity check). The basic configuration had 26 general purpose registers
Processor register
In computer architecture, a processor register is a small amount of storage available as part of a CPU or other digital processor. Such registers are addressed by mechanisms other than main memory and can be accessed more quickly...
and could be expanded to 99 general purpose registers. The general purpose registers had an access time of one microsecond.
The basic configuration had one Computer and could be expanded to a multiprocessor with a second Computer.
The Processor is an independent CPU (with a different instruction set from the Computers) and provides control for 12 to 24 Magnetic drum storage units, four to forty UNISERVO II tape drives, two Electronic page recorders, one or two High-speed printers, and a High-speed punched card reader.
The LARC used core memory banks of 2500 words each, housed four banks per memory cabinet. The basic configuration had eight banks of core (two cabinets), 20000 words. The memory could be expanded to a maximum of 39 banks of core (ten cabinets with one empty bank), 97500 words. The core memory had one parity bit on each digit, for error checking, resulting in 60 bits per memory word. The core memory had an access time of 8 microseconds and a cycle time of 4 microseconds. Each bank operated independently and could begin a new access in any 4 microsecond cycle when it was not already busy. By properly interleaving accesses to different banks the memory could sustain an effective access time of 4 microseconds on each access (e.g., instruction access in one bank data in another).
The data transfer bus connecting the two Computers and the Processor to the core memory was multiplexed to maximize throughput; every 4 microsecond bus cycle was divided into eight 500 nanosecond time slots:
- Processor - instructions and data
- Computer 1 - instructions
- Computer 2 - data
- I/O DMA Synchronizer - data
- Not Used
- Computer 2 - instructions
- Computer 1 - data
- I/O DMA Synchronizer - data
The core memory system enforces a system of interlocks and priorities to avoid simultaneous access of the same memory bank by multiple sections of the system (the Computers, Processor, and I/O DMA Synchronizers) without conflicts or deadlocks. A memory bank is unavailable for one 4 microsecond cycle after being addressed by any section of the system. If another section attempts to address the same memory bank during this time it is locked out and must wait then try again in the next 4 microsecond cycle. To prevent deadlocks and timeouts in the I/O system the following priorities are enforced:
- I/O DMA Synchronizer - Highest
- Processor
- Computers - Lowest
If a higher priority section is locked out in one 4 microsecond cycle, when it tries again in the next 4 microsecond cycle, all lower priority sections are prevented from beginning a new cycle on that memory bank until the higher priority section has completed its access.
The LARC was built using surface barrier transistors, which were already obsolete by the time the first system was delivered. The LARC was a very fast computer for its time. Its addition time was 4 microseconds, multiplication time was 8 microseconds, and the division time was 28 microseconds. It was the fastest computer in 1960-1961, until the IBM 7030
IBM 7030
The IBM 7030, also known as Stretch, was IBM's first transistorized supercomputer. The first one was delivered to Los Alamos National Laboratory in 1961....
took the title.
External links
- Margaret R. Fox Papers, 1935-1976, Charles Babbage InstituteCharles Babbage InstituteThe Charles Babbage Institute is a research center at the University of Minnesota specializing in the history of information technology, particularly the history since 1935 of digital computing, programming/software, and computer networking....
, University of Minnesota. collection contains reports, including the original report on the ENIAC, UNIVAC, and many early in-house National Bureau of Standards (NBS) activity reports; memoranda on and histories of SEAC, SWAC, and DYSEAC; programming instructions for the UNIVAC, LARC, and MIDAC; patent evaluations and disclosures relevant to computers; system descriptions; speeches and articles written by Margaret Fox's colleagues. - Universal Automatic Computer Model LARC
- LARC Manuals and documentation