Intel MIC
Encyclopedia
Intel Many Integrated Core Architecture or Intel MIC (pronouced Mike) is a multiprocessor
computer architecture developed by Intel incorporating earlier work on the Larrabee multicore architecture, the Teraflops Research Chip
multicore chip research project and the Intel Single-chip Cloud Computer
multicore microprocessor.
Prototype products, codenamed Knight's Ferry were announced and released in 2010 to developers including CERN
, Korea Institute of Science and Technology Information (KISTI) and Leibniz Supercomputing Centre. Hardware vendors for prototype boards included IBM, SGI, HP, Dell and others.
A commercial release, codenamed Knight's Corner to be built on a 22nm process
is proposed for release late 2012 to 2013. In September 2011 it was announced that the Texas Advanced Computing Center
(TACC) will use Knight's Corner cards in their 10 PetaFLOPS "Stampede" supercomputer, providing 8 PetaFLOPS of the compute power.
Another contemporary Intel research project implementing x86 architecture on a many-multicore processor was the 'Single Chip Cloud Computer', (prototype introduced 2009.), a design mimicking a cloud computing
computer datacentre on a single chip with multiple independent cores - the prototype design included 48 cores per chip with hardware support for selective frequency and voltage control of cores to maximise energy efficiency, and incorporated a mesh network
for interchip messaging. The design lacked cache coherent cores and focussed on principles that would allow the design to scale to many more cores.
The Teraflops Research Chip (prototype unveiled 2007.) was an experimental 80 core chip with two floating point units per chip implementing a 96-bit VLIW architecture. The project investigated intercore communication methods, per-chip power management, and achieved 1.01 TFLOPS at 3.16 GHz consuming 62 W of power.
The development product was offered as a PCIe card with 32 in-order cores at up to 1.2 GHz with 4 threads per core, 2 GB GDDR5 memory, and 8 MB coherent L2 cache (256 kB per core with 32 kB L1 cache), and a power requirement of ~300 W, built at a 45 nm process. In the Aubrey Isle core a 1,024-bit ring bus (512-bit bi-directional) connects processors to main memory. Single board performance has exceeded 750 GFLOPS. The prototype boards only support single precision floating point instructions.
In June 2011, SGI
announced a partnership with Intel to utilize the MIC architecture in its high performance computing products. In September 2011, it was announced that the Texas Advanced Computing Center
(TACC) will use Knight's Corner cards in their 10 PetaFLOPS "Stampede" supercomputer, providing 8 PetaFLOPS of the compute power. According to "Stampede: A Comprehensive Petascale Computing Environment" the "second generation Intel (Knights Landing) MICs will be added when they become available, increasing Stampede's aggregate peak performance to at least 15 PetaFLOPS."
On November 15, 2011, Intel showed a Knight's Corner processor publicly for the first time. It was an early silicon sample. Intel also demonstrated that it was very functional by setting a world record 1 TeraFLOPS of performance for a general purpose processor. The Knight's Corner demo showed sustained performance of more than a TeraFLOPS on a wide range of DGEMM operations. Intel emphasized during the demonstration this represented sustained TeraFLOPS (not "raw TeraFLOPS" used by others to get higher but less meaningful numbers), and that it was the first general purpose co-processor to ever achieve TeraFLOPS performance.
, OpenCL
, Intel Cilk Plus
and specialised versions of Intel's Fortran, C++ and math libraries.
Design elements inherited from the Larrabee project include x86 ISA, 512-bit SIMD units, coherent L2 cache, and ultra-wide ring bus connecting processors and memory.
Multiprocessor
Computer system having two or more processing units each sharing main memory and peripherals, in order to simultaneously process programs.Sometimes the term Multiprocessor is confused with the term Multiprocessing....
computer architecture developed by Intel incorporating earlier work on the Larrabee multicore architecture, the Teraflops Research Chip
Teraflops Research Chip
The Teraflops Research Chip is a research processor containing 80 cores developed by Intel Corporation's Tera-Scale Computing Research Program. The processor was officially announced February 11, 2007 and shown working at the 2007 International Solid-State Circuits Conference...
multicore chip research project and the Intel Single-chip Cloud Computer
Single-chip Cloud Computer
The Single-chip Cloud Computer is a microprocessor designed by Intel. It is a research chip. Intel designed the chip to investigate the challenges and opportunities of integrating a cloud into a chip....
multicore microprocessor.
Prototype products, codenamed Knight's Ferry were announced and released in 2010 to developers including CERN
CERN
The European Organization for Nuclear Research , known as CERN , is an international organization whose purpose is to operate the world's largest particle physics laboratory, which is situated in the northwest suburbs of Geneva on the Franco–Swiss border...
, Korea Institute of Science and Technology Information (KISTI) and Leibniz Supercomputing Centre. Hardware vendors for prototype boards included IBM, SGI, HP, Dell and others.
A commercial release, codenamed Knight's Corner to be built on a 22nm process
22 nanometer
The 22 nanometer node is the CMOS process step following 32 nm. It was introduced by semiconductor companies in 2011. The typical half-pitch for a memory cell is around 22 nm...
is proposed for release late 2012 to 2013. In September 2011 it was announced that the Texas Advanced Computing Center
Texas Advanced Computing Center
The Texas Advanced Computing Center at the University of Texas at Austin, United States, is a research center for advanced computational science, engineering and technology. TACC is located on UT's J.J. Pickle Research Campus....
(TACC) will use Knight's Corner cards in their 10 PetaFLOPS "Stampede" supercomputer, providing 8 PetaFLOPS of the compute power.
Background
The Larrabee microarchitecture (in development since 2006) introduced very wide (512-bit) SIMD units to a x86 architecture based processor design, extended to a cache coherent multiprocessor system connected via a ring bus to memory; each core was capable of 4-way multi-threading. Due to the design being intended for GPU as well as general purpose computing the Larrabee chips also included specialised hardware for texture sampling. The project to produce a GPU retail product directly from the Larrabee research project was terminated in May 2010.Another contemporary Intel research project implementing x86 architecture on a many-multicore processor was the 'Single Chip Cloud Computer', (prototype introduced 2009.), a design mimicking a cloud computing
Cloud computing
Cloud computing is the delivery of computing as a service rather than a product, whereby shared resources, software, and information are provided to computers and other devices as a utility over a network ....
computer datacentre on a single chip with multiple independent cores - the prototype design included 48 cores per chip with hardware support for selective frequency and voltage control of cores to maximise energy efficiency, and incorporated a mesh network
Mesh networking
Mesh networking is a type of networking where each node must not only capture and disseminate its own data, but also serve as a relay for other nodes, that is, it must collaborate to propagate the data in the network....
for interchip messaging. The design lacked cache coherent cores and focussed on principles that would allow the design to scale to many more cores.
The Teraflops Research Chip (prototype unveiled 2007.) was an experimental 80 core chip with two floating point units per chip implementing a 96-bit VLIW architecture. The project investigated intercore communication methods, per-chip power management, and achieved 1.01 TFLOPS at 3.16 GHz consuming 62 W of power.
Knight's Ferry
Intel's MIC prototype board, named Knight's Ferry, incorporating a processor codenamed Aubrey Isle was announced 31 May 2010. The product was stated to be a derivative of the Larrabee project and other Intel research including the Single-chip Cloud Computer.The development product was offered as a PCIe card with 32 in-order cores at up to 1.2 GHz with 4 threads per core, 2 GB GDDR5 memory, and 8 MB coherent L2 cache (256 kB per core with 32 kB L1 cache), and a power requirement of ~300 W, built at a 45 nm process. In the Aubrey Isle core a 1,024-bit ring bus (512-bit bi-directional) connects processors to main memory. Single board performance has exceeded 750 GFLOPS. The prototype boards only support single precision floating point instructions.
Knight's Corner
The Knight's Corner product is expected to be made at a 22 nm process size, using Intel's Tri-gate technology with more than 50 cores per chip, and is expected to lead to commercial products.In June 2011, SGI
Silicon Graphics International
Silicon Graphics International Corp. , is an American manufacturer of computer hardware and software, including high-performance computing solutions, x86-based servers for datacenter deployment, and visualization products...
announced a partnership with Intel to utilize the MIC architecture in its high performance computing products. In September 2011, it was announced that the Texas Advanced Computing Center
Texas Advanced Computing Center
The Texas Advanced Computing Center at the University of Texas at Austin, United States, is a research center for advanced computational science, engineering and technology. TACC is located on UT's J.J. Pickle Research Campus....
(TACC) will use Knight's Corner cards in their 10 PetaFLOPS "Stampede" supercomputer, providing 8 PetaFLOPS of the compute power. According to "Stampede: A Comprehensive Petascale Computing Environment" the "second generation Intel (Knights Landing) MICs will be added when they become available, increasing Stampede's aggregate peak performance to at least 15 PetaFLOPS."
On November 15, 2011, Intel showed a Knight's Corner processor publicly for the first time. It was an early silicon sample. Intel also demonstrated that it was very functional by setting a world record 1 TeraFLOPS of performance for a general purpose processor. The Knight's Corner demo showed sustained performance of more than a TeraFLOPS on a wide range of DGEMM operations. Intel emphasized during the demonstration this represented sustained TeraFLOPS (not "raw TeraFLOPS" used by others to get higher but less meaningful numbers), and that it was the first general purpose co-processor to ever achieve TeraFLOPS performance.
Knight's Landing
Code name for the second MIC architecture processors from Intel.Design
The basis of the Intel MIC design is to leverage x86 legacy by creating a x86 compatible multiprocessor architecture that can utilise existing paralellisation software tools. Programming tools include OpenMPOpenMP
OpenMP is an API that supports multi-platform shared memory multiprocessing programming in C, C++, and Fortran, on most processor architectures and operating systems, including Linux, Unix, AIX, Solaris, Mac OS X, and Microsoft Windows platforms...
, OpenCL
OpenCL
OpenCL is a framework for writing programs that execute across heterogeneous platforms consisting of CPUs, GPUs, and other processors. OpenCL includes a language for writing kernels , plus APIs that are used to define and then control the platforms...
, Intel Cilk Plus
Intel Cilk Plus
Cilk Plus is an extension to the C and C++ programming languages, designed for multithreaded parallel computing.On July 31, 2009, Cilk Arts, producers of the Cilk++ programming language, announced that its products and engineering team were now part of Intel Corp...
and specialised versions of Intel's Fortran, C++ and math libraries.
Design elements inherited from the Larrabee project include x86 ISA, 512-bit SIMD units, coherent L2 cache, and ultra-wide ring bus connecting processors and memory.