High-level synthesis
Encyclopedia
High-level synthesis, sometimes referred to as C synthesis, electronic system level
(ESL) synthesis, algorithmic synthesis, or behavioral synthesis, is an automated design process that interprets an algorithmic description of a desired behavior and creates hardware that implements that behavior. The starting point of a high-level synthesis flow is ANSI C
/C++
/SystemC
code. The code is analyzed, architecturally constrained, and scheduled to create a register transfer level
hardware design language (HDL), which is then in turn commonly synthesized to the gate level by the use of a logic synthesis
tool. The goal of HLS is to let hardware designers efficiently build and verify hardware, by giving them better control over optimization of their design architecture, and through the nature of allowing the designer to describe the design at a higher level of tools while the tool does the RTL implementation. Verification of the RTL is an important part of the process.
Hardware design can be created at a variety of levels of abstraction. The commonly used levels of abstraction are gate level, register transfer level
(RTL), and algorithmic level.
While logic synthesis
uses an RTL description of the design, high-level synthesis works at a higher level of abstraction, starting with an algorithmic description in a high-level language such as SystemC and Ansi C/C++. The designer typically develops the module functionality and the interconnect protocol. The high-level synthesis tools handle the micro-architecture and transform untimed or partially timed functional code into fully timed RTL implementations, automatically creating cycle-by-cycle detail for hardware implementation. The (RTL) implementations are then used directly in a conventional logic synthesis flow to create a gate-level implementation.
First generation behavioral synthesis was introduced by Synopsys in 1994 as Behavioral Compiler and used Verilog or VHDL as input languages. The abstraction level used was partially timed (clocked) processes. Tools based on behavioral Verilog or VHDL were not widely adopted in part because neither languages nor the partially timed abstraction were well suited to modeling behavior at a high level. 10 years later, in early 2004, Synopsys end-of-lifed Behavioral Compiler.
In 2004, there emerged a number of next generation commercial high-level synthesis products (also called behaviorial synthesis or algorithmic synthesis at the time) which provided synthesis of circuits specified at C level to a register transfer level (RTL) specification. Synthesizing from the popular C language offered accrued abstraction, expressive power and coding flexibility while tying with existing flows and legacy models. This language shift, combined with other technical advances was a key enabler for successful industrial usage. High-level synthesis tools are used for complex ASIC and FPGA design.
High-level synthesis was primarily adopted in Japan and Europe in the early years. As of late 2008, there was an emerging adoption in the United States.
/C++
and SystemC
.
High level synthesis typically also includes a bit-accurate executable specification as input, since to derive an efficient hardware implementation, additional information is needed on what is an acceptable Mean-Square Error or Bit-Error Rate etc. For example, if the designer starts with a FIR filter written using the "double" floating type, before he or she can derive an efficient hardware implementation, they need to perform numerical refinement to arrive at a fixed-point implementation. The refinement requires additional information on the level of quantization noise that can be tolerated, the valid input ranges etc. This bit-accurate specification makes the high level synthesis
source specification functionally complete.
Electronic system level
Electronic system level design and verification is an emerging electronic design methodology that focuses on the higher abstraction level concerns first and foremost. The term Electronic System Level or ESL Design was first defined by Gartner Dataquest, a EDA-industry-analysis firm, on February...
(ESL) synthesis, algorithmic synthesis, or behavioral synthesis, is an automated design process that interprets an algorithmic description of a desired behavior and creates hardware that implements that behavior. The starting point of a high-level synthesis flow is ANSI C
ANSI C
ANSI C refers to the family of successive standards published by the American National Standards Institute for the C programming language. Software developers writing in C are encouraged to conform to the standards, as doing so aids portability between compilers.-History and outlook:The first...
/C++
C++
C++ is a statically typed, free-form, multi-paradigm, compiled, general-purpose programming language. It is regarded as an intermediate-level language, as it comprises a combination of both high-level and low-level language features. It was developed by Bjarne Stroustrup starting in 1979 at Bell...
/SystemC
SystemC
SystemC is a set of C++ classes and macros which provide an event-driven simulation kernel in C++ . These facilities enable a designer to simulate concurrent processes, each described using plain C++ syntax...
code. The code is analyzed, architecturally constrained, and scheduled to create a register transfer level
Register transfer level
In integrated circuit design, register-transfer level is a level of abstraction used in describing the operation of a synchronous digital circuit...
hardware design language (HDL), which is then in turn commonly synthesized to the gate level by the use of a logic synthesis
Logic synthesis
In electronics, logic synthesis is a process by which an abstract form of desired circuit behavior, typically register transfer level , is turned into a design implementation in terms of logic gates. Common examples of this process include synthesis of HDLs, including VHDL and Verilog...
tool. The goal of HLS is to let hardware designers efficiently build and verify hardware, by giving them better control over optimization of their design architecture, and through the nature of allowing the designer to describe the design at a higher level of tools while the tool does the RTL implementation. Verification of the RTL is an important part of the process.
Hardware design can be created at a variety of levels of abstraction. The commonly used levels of abstraction are gate level, register transfer level
Register transfer level
In integrated circuit design, register-transfer level is a level of abstraction used in describing the operation of a synchronous digital circuit...
(RTL), and algorithmic level.
While logic synthesis
Logic synthesis
In electronics, logic synthesis is a process by which an abstract form of desired circuit behavior, typically register transfer level , is turned into a design implementation in terms of logic gates. Common examples of this process include synthesis of HDLs, including VHDL and Verilog...
uses an RTL description of the design, high-level synthesis works at a higher level of abstraction, starting with an algorithmic description in a high-level language such as SystemC and Ansi C/C++. The designer typically develops the module functionality and the interconnect protocol. The high-level synthesis tools handle the micro-architecture and transform untimed or partially timed functional code into fully timed RTL implementations, automatically creating cycle-by-cycle detail for hardware implementation. The (RTL) implementations are then used directly in a conventional logic synthesis flow to create a gate-level implementation.
History
Early academic work extracted scheduling, allocation, and binding as the basic steps for high-level-synthesis. Scheduling partitions the algorithm in control steps that are used to define the states in the FSM. Each control step contains one small section of the algorithm that can be performed in a single clock cycle in the hardware. Allocation and binding maps the instructions and variables to the hardware components, multiplexors, registers and wires of the data path.First generation behavioral synthesis was introduced by Synopsys in 1994 as Behavioral Compiler and used Verilog or VHDL as input languages. The abstraction level used was partially timed (clocked) processes. Tools based on behavioral Verilog or VHDL were not widely adopted in part because neither languages nor the partially timed abstraction were well suited to modeling behavior at a high level. 10 years later, in early 2004, Synopsys end-of-lifed Behavioral Compiler.
In 2004, there emerged a number of next generation commercial high-level synthesis products (also called behaviorial synthesis or algorithmic synthesis at the time) which provided synthesis of circuits specified at C level to a register transfer level (RTL) specification. Synthesizing from the popular C language offered accrued abstraction, expressive power and coding flexibility while tying with existing flows and legacy models. This language shift, combined with other technical advances was a key enabler for successful industrial usage. High-level synthesis tools are used for complex ASIC and FPGA design.
High-level synthesis was primarily adopted in Japan and Europe in the early years. As of late 2008, there was an emerging adoption in the United States.
Source Input
The most common source inputs for high level synthesis are based on standards languages such as ANSI CANSI C
ANSI C refers to the family of successive standards published by the American National Standards Institute for the C programming language. Software developers writing in C are encouraged to conform to the standards, as doing so aids portability between compilers.-History and outlook:The first...
/C++
C++
C++ is a statically typed, free-form, multi-paradigm, compiled, general-purpose programming language. It is regarded as an intermediate-level language, as it comprises a combination of both high-level and low-level language features. It was developed by Bjarne Stroustrup starting in 1979 at Bell...
and SystemC
SystemC
SystemC is a set of C++ classes and macros which provide an event-driven simulation kernel in C++ . These facilities enable a designer to simulate concurrent processes, each described using plain C++ syntax...
.
High level synthesis typically also includes a bit-accurate executable specification as input, since to derive an efficient hardware implementation, additional information is needed on what is an acceptable Mean-Square Error or Bit-Error Rate etc. For example, if the designer starts with a FIR filter written using the "double" floating type, before he or she can derive an efficient hardware implementation, they need to perform numerical refinement to arrive at a fixed-point implementation. The refinement requires additional information on the level of quantization noise that can be tolerated, the valid input ranges etc. This bit-accurate specification makes the high level synthesis
source specification functionally complete.
Process stages
The high-level synthesis process consists of a number of activities. Various high-level synthesis tools perform these activities in different orders using different algorithms. Some high-level synthesis tools combine some of these activities or perform them iteratively to converge on the desired solution.- Lexical processing
- Algorithm optimization
- Control/Dataflow analysis
- Library processing
- Resource allocation
- Scheduling
- Functional unit binding
- Register binding
- Output processing
- Input Rebundling
Architectural constraints
Synthesis constraints for the architecture can automatically be applied based on the design analysis. These constraints can be broken into- Hierarchy
- Interface
- Memory
- Loop
- Low-level timing constraints
- iteration
Interface synthesis
Interface Synthesis refers to the ability to accept pure C/C++ description as its input, then use automated interface synthesis technology to control the timing and communications protocol on the design interface. This enables interface analysis and exploration of a full range of hardware interface options such as streaming, single- or dual-port RAM plus various handshaking mechanisms. With interface synthesis the designer does not embed interface protocols in the source description. Examples might be: direct connection, one line, 2 line handshake, FIFO.See also
- Electronic design automationElectronic design automationElectronic design automation is a category of software tools for designing electronic systems such as printed circuit boards and integrated circuits...
- Electronic system levelElectronic system levelElectronic system level design and verification is an emerging electronic design methodology that focuses on the higher abstraction level concerns first and foremost. The term Electronic System Level or ESL Design was first defined by Gartner Dataquest, a EDA-industry-analysis firm, on February...
- Logic synthesisLogic synthesisIn electronics, logic synthesis is a process by which an abstract form of desired circuit behavior, typically register transfer level , is turned into a design implementation in terms of logic gates. Common examples of this process include synthesis of HDLs, including VHDL and Verilog...
- High level verification
- SystemVerilogSystemVerilogIn the semiconductor and electronic design industry, SystemVerilog is a combined Hardware Description Language and Hardware Verification Language based on extensions to Verilog.-History:...
Vendors
- AutoPilot from AutoESL acquired by Xilinx 1/31/2011 http://www.eetimes.com/electronics-news/4212668/Xilinx-buys-high-level-synthesis-EDA-vendor
- BlueSpec Compiler from Bluespec, Inc.Bluespec, Inc.Bluespec, Inc. is a semiconductor tool design company co-founded by Prof. Arvind of MIT in June 2003. Arvind had previously founded Sandburst in 2000, which specialized in producing chips for 10G-bit Ethernet routers; for this task, Arvind had developed the Bluespec language, a high-level...
- C-to-Silicon from Cadence Design SystemsCadence Design SystemsCadence Design Systems, Inc is an electronic design automation software and engineering services company, founded in 1988 by the merger of SDA Systems and ECAD, Inc...
- Concurrent Acceleration from Concurrent EDA
- Symphony C Compiler from SynopsysSynopsysSynopsys, Inc. is one of the largest companies in the Electronic Design Automation industry. Synopsys' first and best-known product is Design Compiler, a logic-synthesis tool. Synopsys offers a wide range of other products used in the design of an application-specific integrated circuit...
- PowerOpt from ChipVision
- Cynthesizer from Forte Design SystemsForte Design SystemsForte Design Systems, Inc. Forte is a provider of high-level synthesis software products, also known as ESL synthesis or behavioral synthesis that enable design at a higher level of abstraction. Forte's main product is Cynthesizer....
- Catapult CCatapult CCatapult C Synthesis, a commercial electronic design automation product of Mentor Graphics, is a high-level synthesis tool, sometimes called algorithmic synthesis or ESL synthesis...
from Mentor GraphicsMentor GraphicsMentor Graphics, Inc is a US-based multinational corporation dealing in electronic design automation for electrical engineering and electronics, as of 2004, ranked third in the EDA industry it helped create... - CyberWorkBench from NECNEC, a Japanese multinational IT company, has its headquarters in Minato, Tokyo, Japan. NEC, part of the Sumitomo Group, provides information technology and network solutions to business enterprises, communications services providers and government....
- C-to-Verilog from C-to-Verilog.com
- C2R from CebaTech
- CoDeveloper from Impulse Accelerated Technologies
- eXCite from Y Explorations
- LegUP from University of Toronto
- HercuLeS from Nikolaos Kavvadias with free web interface
- hprcARCHITECT from MNB Technologies, Inc.
- PICO from Synfora, acquired by Synopsys in June 2010 http://www.eetimes.com/electronics-news/4200083/Synopsys-buys-Synfora-assets (PICO = Program In/Code Out)